JAJSGN3C December   2018  – December 2022 TPS7A25

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable
      2. 8.3.2 Dropout Voltage
      3. 8.3.3 Current Limit
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 Power Good
      7. 8.3.7 Active Overshoot Pulldown Circuitry
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Functional Mode Comparison
      2. 8.4.2 Normal Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Disabled
        1.       Application and Implementation
          1. 9.1 Application Information
            1. 9.1.1 Adjustable Device Feedback Resistors
            2. 9.1.2 Recommended Capacitor Types
            3. 9.1.3 Input and Output Capacitor Requirements
            4. 9.1.4 Reverse Current
            5. 9.1.5 Feed-Forward Capacitor (CFF)
            6. 9.1.6 Power Dissipation (PD)
            7. 9.1.7 Estimating Junction Temperature
            8. 9.1.8 Special Consideration for Line Transients
          2. 9.2 Typical Application
            1. 9.2.1 Design Requirements
            2. 9.2.2 Detailed Design Procedure
              1. 9.2.2.1 Transient Response
              2. 9.2.2.2 Selecting Feedback Divider Resistors
              3. 9.2.2.3 Thermal Dissipation
            3. 9.2.3 Application Curve
          3. 9.3 Power Supply Recommendations
          4. 9.4 Layout
            1. 9.4.1 Layout Guidelines
            2. 9.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRV|6
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

specified at TJ = –40°C to + 125°C, VIN = VOUT(nom) + 0.5 V or VIN = 2.4 V (whichever is greater), FB tied to OUT, IOUT = 1 mA, VEN = 2 V, and CIN = 1 μF, COUT = 2.2 μF ceramic (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO(RISING) UVLO threshold rising VIN rising 1.95 2.15 2.35 V
VUVLO(HYS) UVLO hysteresis 70 mV
VUVLO(FALLING) UVLO threshold falling VIN falling 1.85 2.09 2.25 V
VFB Feedback voltage Adjustable version only 1.24 V
VOUT Output voltage accuracy Adjustable version, VOUT = VFB 1.228 1.24 1.252 V
VOUT Output voltage accuracy Fixed output versions –1 1 %
ΔVOUT(ΔVIN) Line regulation(1) (VOUT(nom) + 0.5 V or 2.4 V) ≤ VIN ≤ 18 V –0.1 0.1 %
ΔVOUT(ΔIOUT) Load regulation 1 mA ≤ IOUT ≤ 300 mA –0.5 0.5 %
VDO Dropout voltage(2) IOUT = 50 mA 64 105 mV
IOUT = 150 mA 120 180
IOUT = 300 mA 210 340
ICL Output current limit VOUT = 0.9 × VOUT(nom) 325 510 720 mA
IGND Ground pin current IOUT = 0 mA 2 4.5 µA
IOUT = 1 mA 15
ISHUTDOWN Shutdown current VEN ≤ 0.4 V, VIN = 2.4 V, Iout = 0 mA 325 600 nA
IFB FB pin current 10 nA
IEN EN pin current VEN = 18 V 10 nA
VEN(HI) Enable pin high-level input voltage Device enabled 0.9 V
VEN(LOW) Enable pin low-level input voltage Device disabled 0.4 V
VIT(PG,RISING) PG pin threshold rising RPULLUP = 10 kΩ, VOUT rising,
VIN ≥ VUVLO(RISING)		 93 96.5 %VOUT
VHYS(PG) PG pin hysteresis RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)		 3 %VOUT
VIT(PG,FALLING) PG pin threshold falling RPULLUP = 10 kΩ, VOUT falling,
VIN ≥ VUVLO(RISING)		 84 90 %VOUT
VOL(PG) PG pin low level output voltage VOUT < VIT(PG,FALLING), IPG-SINK = 500 µA 0.4 V
ILKG(PG) PG pin leakage current VOUT > VIT(PG,RISING), VPG = 18 V 5 300 nA
PSRR Power-supply rejection ratio f = 10 Hz 75 dB
f = 100 Hz 62
f = 1 kHz 52
Vn Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 1.2 V 300 μVRMS
TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing 165 °C
TSD(reset) Thermal shutdown reset temperature Reset, temperature decreasing 145 °C
(1) Vout(nom) + 0.5 V or 2.4 V (whichever is greater).
(2) VDO is measured with VIN = 0.97 × VOUT(nom) for fixed output voltage versions. VDO is not measured for fixed output voltage versions when VOUT ≤ 2.5 V. For the adjustable output device, VDO is measured with VFB = 0.97 × VFB(nom).