SBVS163A June   2011  – May 2015 TPS7A3401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable Pin Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Operation
      2. 8.1.2 Transient Response
      3. 8.1.3 Post DC-DC Converter Filtering
      4. 8.1.4 Power for Precision Analog
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Recommendations
          1. 8.2.2.1.1 Input and Output Capacitor Requirements
          2. 8.2.2.1.2 Feed-Forward Capacitor Requirements
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

10 Layout

10.1 Layout Guidelines

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.

The GND pin should be tied directly to the PowerPAD under the IC. The PowerPAD should be connected to any internal PCB ground planes using multiple vias directly under the IC.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize performance and ensure stability. Every capacitor (CIN, COUT, CFF) must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because these circuits may impact system performance negatively, and even cause instability.

10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve AC performance (such as PSRR, output noise, and transient response), TI recommends designing the board with separate ground planes for VIN and VOUT, with each ground plane star connected only at the GND pin of the device.

10.2 Layout Example

TPS7A3401 pcb_layout_dgn_bvs163.gif
NOTE: CIN and COUT are size 1208 capacitors, while R1 and R2 are size 0402.
Figure 24. PCB Layout Example (DGN Package)

10.3 Thermal Considerations

Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to a maximum of 125°C. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A3401 device has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A3401 device into thermal shutdown degrades device reliability.

10.4 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data or JEDEC low- and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by the product of the output current times the voltage drop across the output pass element, as shown in Equation 5.

Equation 5. TPS7A3401 q_pd_bvs125.gif

Power dissipation that results from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit.

Figure 25 shows the maximum ambient temperature versus the power dissipation of the TPS7A3401 device. Figure 25 presumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation, having a thorough understanding of the board temperature and thermal impedances is helpful to ensure the TPS7A3401 device does not operate above a junction temperature of 125°C.

TPS7A3401 ai_typ_char_max_ta_dissipation_bvs163.gifFigure 25. Maximum Ambient Temperature (°C) vs Power Dissipation

Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than RθJA. The junction temperature can be estimated with Equation 6.

Equation 6. TPS7A3401 q_new_metrics_bvs066.gif

where

  • PD is the power dissipation shown by Equation 5,
  • TT is the temperature at the center-top of the IC package,
  • TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.

NOTE

Both TT and TB can be measured on actual application boards using a thermo‐gun (an infrared thermometer).

For more information about measuring TT and TB, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com.