JAJSQ32A August 2023 – January 2024 TPS7A53B
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VFB | Feedback voltage | 0.5 | V | |||
VNR/SS | NR/SS pin voltage | 0.5 | V | |||
VUVLO+(IN) | Rising input supply UVLO with BIAS | VIN rising with VBIAS = 3V | 1.02 | 1.085 | V | |
VUVLO-(IN) | Falling input supply UVLO with BIAS | VIN falling with VBIAS = 3V | 0.55 | 0.7 | V | |
VUVLO+(IN) | Rising input supply UVLO without BIAS | VIN rising | 1.31 | 1.39 | V | |
VUVLO-(IN) | Falling input supply UVLO without BIAS | VIN falling | 0.65 | 1.057 | V | |
VUVLO+(BIAS) | Rising bias supply UVLO | VBIAS rising, VIN = 1.1V | 2.83 | 2.9 | V | |
VUVLO-(BIAS) | Falling bias supply UVLO | VBIAS falling, VIN = 1.1V | 2.45 | 2.54 | V | |
VOUT | Output voltage range | 0.5 | 5.15 | V | ||
Output voltage accuracy | 1.4 V ≤ VIN ≤ 6.5 V, 0.5V ≤ VOUT ≤ 5.15V, 5mA ≤ IOUT ≤ 3A |
-0.75 | 0.75 | % | ||
VIN =1.1V, 5mA ≤ IOUT ≤ 3A, 3V ≤ VBIAS ≤ 6.5V |
-0.5 | 0.5 | ||||
ΔVOUT/ΔVIN | Line regulation | IOUT = 5mA, 1.4V ≤ VIN ≤ 6.5V |
0.03 | mV/V | ||
ΔVOUT/ΔIOUT | Load regulation | 5mA ≤ IOUT ≤ 3A 3V ≤ VBIAS ≤ 6.5V VIN = 1.1V |
0.07 | mV/A | ||
5mA ≤ IOUT ≤ 3A | 0.012 | mV/A | ||||
VOS | Error amplifier offset voltage | VIN = 1.4V, IOUT = 5mA | -2.5 | 2.5 | mV | |
VDO | Dropout voltage | VIN = 1.4V, IOUT = 3A, VFB = 0.5V – 3% |
105 | 175 | mV | |
VIN = 5.4V, IOUT = 3A, VFB = 0.5V – 3% |
170 | 280 | ||||
VIN = 5.6V, IOUT = 3A, VFB = 0.5V – 3% |
215 | 375 | ||||
VIN = 1.1V, 3.0V ≤ VBIAS ≤ 6.5V, IOUT = 3A, VFB = 0.5V – 3% |
60 | 110 | ||||
ILIM | Output current limit | VOUT forced at 0.9 × VOUT(nom), VOUT(nom) = 5.0V |
3.6 | 4.2 | 4.9 | A |
ISC | Short-circuit current limit | RLOAD = 20mΩ | 2 | |||
IGND | GND pin current | VIN = 6.5V, IOUT = 5mA | 3 | 4.3 | mA | |
VIN = 1.4 V, IOUT = 3 A | 4.3 | 5.5 | ||||
Shutdown, PG = open, VIN = 6.5V, VEN = 0.5V |
25 | µA | ||||
IEN | EN pin current | VIN = 6.5V, VEN = 0V and 6.5V |
0.5 | µA | ||
IBIAS | BIAS pin current | VIN = 1.1V, VBIAS = 6.5V, VOUT(nom) = 0.5V, IOUT = 3A |
2.3 | 3.5 | mA | |
VIL(EN) | EN pin low-level input voltage (disable device) | 0 | 0.5 | V | ||
VIH(EN) | EN pin high-level input voltage (enable device) | 1.1 | 6.5 | V | ||
VIT-(PG) | Falling PG pin threshold | For falling VOUT | 80% × VOUT | 86% × VOUT | 91% × VOUT | V |
VIT+(PG) | Rising PG pin threshold | For rising VOUT | 85% × VOUT | 91% × VOUT | 96% × VOUT | V |
VOL(PG) | PG pin low-level output voltage | VOUT < VIT(PG), IPG = –1mA (current into device) |
0.4 | V | ||
Ilkg(PG) | PG pin leakage current | VOUT > VIT(PG), VPG = 6.5V | 1 | µA | ||
INR/SS | NR/SS pin charging current | VNR/SS = GND, VIN = 6.5V | 4 | 6.2 | 9 | µA |
IFB | FB pin leakage current | VIN = 6.5V | 100 | nA | ||
RNR | NR resistor value | 250 | kΩ | |||
PSRR | Power-supply rejection ratio | VIN = 1.1V, VOUT = 0.5V, VBIAS = 5V, IOUT = 3A, CNR/SS = 10nF, CFF = 10nF, COUT = 47µF || 10µF || 10µF, f = 10kHz |
53 | dB | ||
VIN = 1.1V, VOUT = 0.5V, VBIAS = 5V, IOUT = 3A, CNR/SS = 10nF, CFF = 10nF, COUT = 47µF || 10µF || 10µF, f = 500kHz |
48 | |||||
Vn | Output noise voltage | Bandwidth = 10Hz to 100kHz, VIN = 1.1V, VOUT = 0.5V, VBIAS = 5V, IOUT = 3A, CNR/SS = 10nF, CFF = 10nF, COUT = 47µF || 10µF || 10µF |
4.6 | µVRMS | ||
Bandwidth = 10Hz to 100kHz, VOUT = 5V, IOUT = 3A, CNR/SS = 10nF, CFF = 10nF, COUT = 47µF || 10µF || 10µF |
13.9 | |||||
Tsd+ | Thermal shutdown temperature increasing | Shutdown, temperature increasing | 160 | °C | ||
Tsd- | Thermal shutdown temperature decreasing | Reset, temperature decreasing | 140 |