JAJSI66A November   2019  – March 2020 TPS7A54

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      デジタル負荷の電源
      2.      RFコンポーネントの電源
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Regulation Features
        1. 8.3.1.1 DC Regulation
        2. 8.3.1.2 AC and Transient Response
      2. 8.3.2 System Start-Up Features
        1. 8.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 8.3.2.2 Internal Sequencing
          1. 8.3.2.2.1 Enable (EN)
          2. 8.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 8.3.2.2.3 Active Discharge
        3. 8.3.2.3 Power-Good Output (PG)
      3. 8.3.3 Internal Protection Features
        1. 8.3.3.1 Foldback Current Limit (ICL)
        2. 8.3.3.2 Thermal Protection (Tsd)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Regulation
      2. 8.4.2 Disabled
      3. 8.4.3 Current Limit Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Recommended Capacitor Types
        1. 9.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 9.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 9.1.1.3 Feed-Forward Capacitor (CFF)
      2. 9.1.2  Soft Start and Inrush Current
      3. 9.1.3  Optimizing Noise and PSRR
      4. 9.1.4  Charge Pump Noise
      5. 9.1.5  Current Sharing
      6. 9.1.6  Adjustable Operation
      7. 9.1.7  Power-Good Operation
      8. 9.1.8  Undervoltage Lockout (UVLO) Operation
      9. 9.1.9  Dropout Voltage (VDO)
      10. 9.1.10 Device Behavior During Transition From Dropout Into Regulation
      11. 9.1.11 Load Transient Response
      12. 9.1.12 Reverse Current Protection Considerations
      13. 9.1.13 Power Dissipation (PD)
      14. 9.1.14 Estimating Junction Temperature
      15. 9.1.15 TPS7A54EVM Thermal Analysis
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V(1), OUT connected to 50 Ω to GND, VEN = 1.1 V, CIN = 10 µF, COUT = 47 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up toVIN with 100 kΩ, unless otherwise noted; typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage 0.8 V
VNR/SS NR/SS pin voltage 0.8 V
VUVLO+(IN) Rising input supply UVLO with BIAS VIN rising with VBIAS = 3 V 1.02 1.085 V
VUVLO-(IN) Falling input supply UVLO with BIAS VIN falling with VBIAS = 3 V 0.55 0.7 V
VUVLO+(IN) Rising input supply UVLO without BIAS VIN rising 1.31 1.39 V
VUVLO-(IN) Falling input supply UVLO without BIAS VIN falling 0.65 1.057 V
VUVLO+(BIAS) Rising bias supply UVLO VBIAS rising, VIN = 1.1 V 2.83 2.9 V
VUVLO-(BIAS) Falling bias supply UVLO VBIAS falling, VIN = 1.1 V 2.45 2.54 V
VOUT Output voltage range 0.8 5.1 V
Output voltage accuracy 1.4 V ≤ VIN ≤ 6.5 V,
0.8 V ≤ VOUT ≤ 5.1 V,
5 mA ≤ IOUT ≤ 4 A		 -0.75 0.75 %
VIN =1.1 V,
5 mA ≤ IOUT ≤ 4 A,
3 V ≤ VBIAS ≤ 6.5 V		 -0.5 0.5
DVOUT/ΔVIN Line regulation IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.03 mV/V
DVOUT/ΔVIN Load regulation 5 mA ≤ IOUT ≤ 4 A,
3 V ≤ VBIAS ≤ 6.5 V, VIN = 1.1 V		 0.07 mV/A
5 mA ≤ IOUT ≤ 4 A 0.012
VOS Error amplifier offset voltage VIN = 1.4V, IOUT = 5mA;
-40℃ ≤ TJ ≤ +125℃		 -2.5 2.5 mV
VDO Dropout voltage VIN = 1.4 V, IOUT = 4 A,
VFB = 0.8 V – 3%		 140 235 mV
VIN = 5.5 V, IOUT = 4 A,
VFB = 0.8 V – 3%		 250 415
VIN = 5.7 V, IOUT = 4 A,
VFB = 0.8 V – 3%		 330 565
VIN = 1.1 V,
3.0 V ≤ VBIAS ≤ 6.5 V, IOUT = 4 A,
VFB = 0.8 V – 3%		 85 175
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V		 4.6 5.2 5.9 A
ISC Short-circuit current limit RLOAD = 20 mΩ 2 A
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 2.8 4 mA
VIN = 1.4 V, IOUT = 4 A 4.8 6
Shutdown, PG = open, VIN = 6.5 V,
VEN = 0.5 V		 25 µA
IEN EN pin current VIN = 6.5 V,
VEN = 0 V and 6.5 V		 0.5 µA
IBIAS BIAS pin current VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 4 A		 2.3 3.5 mA
VIL(EN) EN pin low-level input voltage (disable device) 0 0.5 V
VIH(EN) EN pin high-level input voltage (enable device) 1.1 6.5 V
VIT-(PG) Falling PG pin threshold For falling VOUT 82% × VOUT 88.3% × VOUT 93% × VOUT V
VIT+(PG) Rising PG pin threshold For rising VOUT 84% × VOUT 89.3% × VOUT 95% × VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG),
IPG = –1 mA (current into device)		 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VIN = 6.5 V 4 6.2 9 µA
IFB FB pin leakage current VIN = 6.5 V 100 nA
RNR NR resistor value 250 kΩ
PSRR Power-supply rejection ratio VIN – VOUT = 0.5 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 4 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 µF || 10 µF || 10 µF,
f = 10 kHz		 42 dB
VIN – VOUT = 0.5 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 4 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 µF || 10 µF || 10 µF,
f = 500 kHz		 39
Vn Output noise voltage Bandwidth = 10 Hz to 100 kHz,
VIN = 1.1 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 4 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 µF || 10 µF || 10 µF		 4.4 µVRMS
Bandwidth = 10 Hz to 100 kHz,
VOUT = 5 V, IOUT = 4 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 µF || 10 µF || 10 µF		 8.4
Tsd+ Thermal shutdown temperature increasing Shutdown, temperature increasing 160 °C
Tsd- Thermal shutdown temperature decreasing Reset, temperature decreasing 140 °C
(1) VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the expected VOUT value set by the external feedback resistors.