JAJSFH9J March   2010  – March 2020 TPS7A60-Q1 , TPS7A61-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      プログラム可能なリセット遅延オプション
      2.      イネーブル・オプション
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Reset Delay and Reset Output
      2. 8.3.2 Charge Pump Operation
      3. 8.3.3 Undervoltage Shutdown
      4. 8.3.4 Low-Voltage Tracking
      5. 8.3.5 Integrated Fault Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
      2. 8.4.2 Sleep Mode (TPS7A61-Q1 Only)
      3. 8.4.3 Regulation Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS7A60-Q1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Capacitor
          2. 9.2.1.2.2 Output Capacitor
        3. 9.2.1.3 Application Curve
      2. 9.2.2 TPS7A61-Q1 Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Dissipation and Thermal Considerations
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Reset Delay and Reset Output

Reset delay is implemented when the device starts up to indicate that output voltage is stable and in regulation, and also when the output recovers from a negative voltage spike due to a load step or a dip in the input voltage for a specified duration. The reset-delay timer is initialized when the voltage at the output (VOUT) exceeds 93% of the regulated output voltage (3.3 V or 5 V, as applicable). The reset output (nRST) is asserted high after the power-on-reset delay (tPOR) has elapsed. If the regulated output voltage falls below 93% of the set level, nRST is asserted low after a short de-glitch time of approximately 5.5 µs (typical).

For TPS7A60-Q1 devices, the reset-delay time can be programmed by connecting an external capacitor (CDLY) to the RDELAY pin. The delay time is given by Equation 1:

Equation 1. TPS7A60-Q1 TPS7A61-Q1 eq_tpor_lvsa62.gif

where

  • tPOR = reset delay time in seconds
  • CDLY = reset delay capacitor value in farads, 100 pF to 100 nF

In TPS7A61xx devices, there is no RDELAY pin, and the reset-delay time is preset internally (250 µs typical).

During power up, the regulator incorporates a protection scheme to limit the current through the pass element and output capacitor. When the input voltage exceeds a certain threshold (VIN(POWERUP)) level, the output voltage begins to ramp as shown in Figure 16 and Figure 17. When the output voltage reaches the power-on-reset threshold (VTH(POR)) level, a constant output current charges an external capacitor (CDLY) to an internal threshold (VTH(RDELAY)) voltage level. Then, nRST is asserted high and CDLY is discharged through an internal load. This allows CDLY to charge from approximately 0 V during the next power cycle. If no external capacitor is connected, the delay time is preset internally. This is shown in Figure 16.

In TPS7A60-Q1 devices, if the CDLY capacitor is not connected to the RDELAY pin, the reset-delay time is set internally. This is shown in Figure 17.

TPS7A60-Q1 TPS7A61-Q1 powerup_reset_delay_with_cdly_lvsa62.gifFigure 16. Power Up and Reset-Delay Function With the CDLY Capacitor Connected to the RDELAY Pin for TPS7A60-Q1
TPS7A60-Q1 TPS7A61-Q1 powerup_reset_delay_without_cdly_lvsa62.gifFigure 17. Power Up and Reset Delay Function With the CDLY Capacitor Not Connected or Available in TPS7A60-Q1 and TPS7A61-Q1, Respectively

In case of negative transients in the input voltage (VIN), the reset signal is asserted low only if the output (VOUT) drops and stays below the reset threshold level (VTH(POR)) for more than the de-glitch time (tDEGLITCH). This is shown in Figure 18.

While nRST is low, if the input voltage returns to the nominal operating voltage, the normal power-up sequence is followed. nRST is asserted high, only if the output voltage exceeds the reset-threshold voltage (VTH(POR)) and the reset-delay time (tPOR) has elapsed. This is shown in the shaded region of Figure 18.

TPS7A60-Q1 TPS7A61-Q1 conditions_activation_reset_lvsa62.gifFigure 18. Conditions for Activation of Reset