JAJSFH8G June   2011  – March 2020 TPS7A63-Q1 , TPS7A6401-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      固定出力電圧オプション
      2.      可変出力電圧オプション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Power Up, Reset Delay, and Reset Output
      2. 7.3.2  Adjustable Output Voltage
      3. 7.3.3  Chip Enable
      4. 7.3.4  Charge Pump Operation
      5. 7.3.5  Low-Power Mode
      6. 7.3.6  Undervoltage Shutdown
      7. 7.3.7  Low-Voltage Tracking
      8. 7.3.8  Integrated Fault Protection
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Integrated Window Watchdog
        1. 7.3.10.1 Programmable-Window Watchdog
        2. 7.3.10.2 Watchdog Enable
        3. 7.3.10.3 Watchdog Service Signal
        4. 7.3.10.4 Watchdog Fault Outputs
        5. 7.3.10.5 Watchdog Initialization
        6. 7.3.10.6 Watchdog Operation
        7. 7.3.10.7 Watchdog Fault Conditions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN Lower Than 4 V
      2. 7.4.2 Operation With VIN Larger Than 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Example
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Using the TPS7A6333-Q1 or TPS7A6350-Q1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application Using the TPS7A6401-Q1
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation and Thermal Considerations
        1. 10.1.1.1 Example
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VIN = 14 V, TJ = –40ºC to 150ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN PIN)
VIN Input voltage VOUT = 2.5 V to 7 V, IOUT = 1 mA 7(1) 40 V
IQUIESCENT Quiescent current VIN = 8.2 V to 18 V, VEN = 5 V,
IOUT = 0.01 mA to 0.75 mA		 35 µA
ISLEEP Sleep or shutdown current VIN = 8.2 V to 18 V, VEN < 0.8 V,
IOUT = 0 mA (no load), TA = 125°C		 3 µA
VIN-UVLO Undervoltage lockout voltage Ramp VIN down until output is turned OFF 3.16 V
VIN(POWERUP) Power-up voltage Ramp VIN up until output is turned ON 3.45 V
DEVICE ENABLE INPUT (EN PIN)
VIL Logic-input low level 0 0.8 V
VIH Logic-input high level 2.5 40 V
REGULATED OUTPUT VOLTAGE (VOUT PIN)
VOUT Regulated output voltage Fixed VOUT value (3.3 V, 5 V or a programmed value),
IOUT = 10 mA to 200 mA, VIN = VOUT + 1 V to 16 V 		–2% 2%
ΔVLINE-REG Line regulation VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 5 V 15 mV
VIN = 6 V to 28 V, IOUT = 10 mA, VOUT = 3.3 V 20
ΔVLOAD-REG Load regulation IOUT = 10 mA to 200 mA, VIN = 14 V, VOUT = 5 V 25 mV
IOUT = 10 mA to 200 mA, VIN = 14 V, VOUT = 3.3 V 35
VDROPOUT
Dropout voltage
(VIN – VOUT)		 IOUT = 200 mA 500 mV
IOUT = 150 mA 300
RSW(2) Switch resistance VIN to VOUT resistance 2 Ω
IOUT Output current VOUT in regulation 0 200 mA
[VOUT in regulation, VOUT = 3.3 V, VIN = 6 V](4) 0 300
ICL Output current limit VOUT = 0 V (VOUT pin is shorted to ground) 350 1000 mA
PSRR(3) Power-supply ripple rejection VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA, frequency = 100 Hz, VOUT = 5 V and VOUT = 3.3 V 60 dB
VIN-RIPPLE = 0.5 Vpp, IOUT = 200 mA, frequency = 150 kHz, VOUT = 5 V and VOUT = 3.3 V 30
RESET (nRST PIN)
VOL Reset pulled low IOL = 5 mA 0.4 V
IOH Leakage current Reset pulled to VOUT through a 5-kΩ resistor 1 µA
VTH(POR) Power-on-reset threshold VOUT powered up above internally set tolerance,
VOUT = 5 V		 4.5 4.65 4.77 V
VOUT powered up above internally set tolerance,
VOUT = 3.3 V 		3.07
UVTHRES Reset threshold VOUT falling below internally set tolerance,
VOUT = 5 V		 4.5 4.65 4.77 V
VOUT falling below internally set tolerance,
VOUT = 3.3 V		 3.07
tPOR(4) Power-on-reset delay CDLY = 100 pF 300 µs
CDLY = 100 nF 300 ms
tPOR-PRESET Internally preset
Power-on-reset delay		 CDLY not connected, VOUT = 5 V and VOUT = 3.3 V 250 µs
tDEGLITCH Reset deglitch time 5.5 µs
RESET DELAY (RDELAY PIN)
VTH(RDELAY)
Threshold to release nRST high Voltage at RDELAY pin is ramped up 3 3.3 V
IDLY Delay capacitor
charging current		 0.75 1 1.25 µA
IOL Delay capacitor
discharging current		 Voltage at RDELAY pin = 1 V 5 mA
CURRENT VOLTAGE REFERENCE (ROSC PIN)
VROSC Voltage reference 0.95 1 1.05 V
WATCHDOG FAULT / FLAG OUTPUT (WD_FLT / WD_FLAG Pin)
VOL Logic output low level IOL= 5 mA 0.4 V
IOH Leakage current WD_FLT/WD_FLG pulled to VOUT through 5-kΩ resistor 1 µA
WATCHDOG ENABLE INPUT (nWD_EN PIN)
VIL Logic input low level 0.8 V
VIH Logic input high level 3 V < VDD < 5.25 V 2.5 V
WATCHDOG INPUT PULSE (WD PIN)
VIL Logic input low level 0.8 V
VIH Logic input high level 3 V < VDD < 5.25 V 2.5 V
tWD Watchdog window duration ROSC = 10 kΩ ± 1% 10 ms
ROSC = 20kΩ ± 1% 20
tWD-tol Tolerance of watchdog period using external resistor Excludes tolerance of ROSC
(external resistor connected to ROSC pin)		 –10% 10%
tWD-DEFAULT Default watchdog period External resistor not connected, ROSC pin is floating or open 108 164 254 ms
tWD-HOLD Minimum pulse width for resetting watch dog timer 1.65 µs
OPERATING TEMPERATURE RANGE
TJ Operating junction temperature –40 150 ºC
TSHUTDOWN Thermal shutdown trip point 165 ºC
THYST Thermal shutdown hysteresis 10 ºC
(1) VIN can go down to 4 V for 130 ms or less and remain functional. If VIN is less than 7 V for longer than 130 ms, then some devices can turn off until the input voltage rises above 7 V.
(2) This test is done with VOUT in regulation, measuring the VIN – VOUT parameter when VOUT drops by 100 mV from the programmed value (of VOUT) at specified loads.
(3) Specified by design - not tested.
(4) Design Information - not tested; specified by characterization.