JAJSC95F December 2012 – December 2017 TPS7A66-Q1 , TPS7A69-Q1
PRODUCTION DATA.
An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this pin is open, the default delay time is 290 µs (typ). After releasing the PG pin high, the capacitor on this pin discharges, thus allowing the capacitor to charge from approximately 0.2 V for the next power-on-reset delay-timer function.
An external capacitor, CT, defines the reset-pulse delay time, t(POR), with the charge time of:
The power-on reset initializes once the output VOUT exceeds 91.6% of the programmed value. The power-on-reset delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG pin high.