JAJSC95F December   2012  – December 2017 TPS7A66-Q1 , TPS7A69-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハードウェア・イネーブル・オプション
      2.      入力電圧センス・オプション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Regulated Output (VOUT)
      3. 7.3.3 Power-On Reset (PG)
      4. 7.3.4 Reset Delay Timer (CT)
      5. 7.3.5 Sense Comparator (SI and SO for TPS7A69-Q1)
      6. 7.3.6 Adjustable Output Voltage (FB for TPS7A6601-Q1)
      7. 7.3.7 Undervoltage Shutdown
      8. 7.3.8 Low-Voltage Tracking
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
      3. 7.4.3 Operation With V(VinUVLO)< VIN < VIN(min)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS7A66-Q1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
        3. 8.2.1.3 Application Curve
      2. 8.2.2 TPS7A69-Q1 Typical Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Low-Voltage Tracking Threshold
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
    3. 10.3 Power Dissipation and Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VIN = 14 V, 1 mΩ < ESR < 2 Ω, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (VIN)
VIN Input voltage Fixed 5-V output, IO = 1 mA 5.5 40 V
Fixed 3.3-V output, IO = 1 mA 4 40
I(q) Quiescent current VIN = 5.5 V to 40 V, EN = ON, IO = 0.2 mA 12 20 µA
I(Sleep) Input sleep current No load current and EN = OFF 4 µA
I(EN) EN pin current V(EN) = 40 V 1 µA
V(bg) Band gap Reference voltage for FB 1.199 1.223 1.247 V
V(VinUVLO) Undervoltage lockout detection Ramp VIN down until output turns OFF 2.6 V
V(UVLOhys) Undervoltage hysteresis 1 V
ENABLE INPUT (EN)
VIL Logic input low level 0 0.4 V
VIH Logic input high level 1.7 V
REGULATED OUTPUT (VOUT)
VOUT Regulated output IO = 1 mA, TJ = 25°C –1% 1%
VIN = 6 V to 40 V, IO = 1 mA to 150 mA, fixed 5-V version –2% 2%
VIN = 4 V to 40 V, IO = 1 mA to 150 mA, fixed 3.3-V version –2% 2%
VIN = VOUT + 0.45 V and Vin ≥ 4 V, IO = 1 mA to 150 mA, adjustable version(1) –2% 2%
V(line-reg) Line regulation VIN = 5.5 V to 40 V, IO = 50 mA 5 mV
V(load-reg) Load regulation IO = 1 mA to 150 mA 20 mV
V(dropout) Dropout voltage V(dropout) = VIN – VOUT, IOUT = 80 mA 180 240 mV
VIN – VOUT, IOUT = 150 mA 300 450
VIN = 3 V, V(dropout) = VIN – VOUT, IO = 5 mA 12 27.5 58
VIN = 3 V, V(dropout) =VIN –VOUT, IO = 30 mA 44 80 145
IO Output current VOUT in regulation 0 150 mA
I(lreg-CL) Output current limit VOUT short to ground 500 800 mA
PSRR Power supply ripple rejection(2) VIN = 12 V, IL = 10 mA, output capacitance = 2.2 µF dB
Frequency = 100 Hz 60
Frequency = 100 kHz 40
VOLTAGE SENSING PRE-WARNING
VI(S-th) Sense low threshold V(SI) decreasing 1.089 1.123 1.157 V
VI(S-th,hys) Sense threshold hysteresis 50 100 150 mV
VOL(S) Sense output low voltage (V(SI) ≤ 1.06 V, VIN ≥ 4 V, R(SO) = 10 kΩ to VOUT 0.4 V
IOH(S) Sense output leakage (V(SO) = 5 V, V(SI) ≥ 1.5 V) 1 µA
II(S) Sense input current –1 0.1 1 µA
RESET (PG)
VOL Reset output, low voltage IOL = 0.5 mA 0.4 V
Ilkg Leakage current Reset pulled up to VOUT through a 10-kΩ resistor 1 µA
V(TH-POR) Power-on-reset threshold VOUT increasing 89.6 91.6 93.6 % of VOUT
V(Thres) Hysteresis 2 % of VOUT
RESET DELAY (CT)
I(Chg) Delay-capacitor charging current VCT = 0 V 1.4 µA
V(th) CT threshold to release PG high 1 V
OPERATING TEMPERATURE RANGE
TJ Junction temperature –40 150 °C
T(shutdown) Junction shutdown temperature 175 °C
T(hyst) Hysteresis of thermal shutdown 20 °C
(1) Adjustable version with precision external feedback resistor with tolerance of less than ±1%.
(2) Design information – not tested.