SBVS209D May   2013  – April 2017 TPS7A7002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable (EN)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Capacitor (IN)
      2. 8.1.2 Output Capacitor (OUT)
      3. 8.1.3 Feedback Resistors (FB)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

For best performance, place all circuit components on the same side of the circuit board, and place the external components as close to the device as practically possible. The use of vias and long traces is strongly discouraged because of parasitics that might affect performance; follow these guidelines to minimize parasitics. Also, embed a ground reference plane to maintain accuracy of the output voltage and shield noise. Make sure that this plane is connected to the PowerPAD in order to help spread (or sink) heat from the device; be aware that NC pins might be connected to this plane. The recommended layout is shown in Figure 10.

10.2 Layout Example

TPS7A7002 TPS7A7002Layout.gif Figure 10. Layout Recommendation

10.3 Thermal Consideration

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is re-enabled.

The internal protection circuitry of the TPS7A7002 is designed to protect against overload conditions. The protection circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A7002 into thermal shutdown degrades device reliability.

10.4 Power Dissipation

Power dissipation (PD) of the device depends on the input voltage and load conditions, and is calculated using Equation 3.

Equation 3. TPS7A7002 q_pd_bvs064.gif

In order to minimize power dissipation and achieve greater efficiency, use the lowest possible input voltage necessary to achieve the required output voltage regulation

On the SOIC (DDA) package, the primary conduction path for heat is through the exposed pad to the PCB. The pad can either be connected to ground or left floating; however, attach the pad to an appropriate amount of copper PCB area to prevent the device from overheating. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device, and is calculated using Equation 4:

Equation 4. TPS7A7002 q_rth__bvs136.gif