JAJSM31 May   2022 TPS7A74

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Global Undervoltage Lockout (UVLO) Circuit
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimating Junction Temperature
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.3 Application Curves

GUID-2848BD8B-2D2A-49D1-B586-89F5601EBFA1-low.gifFigure 8-3 VBIAS Line Transient
GUID-20220315-SS0I-0PMT-9XQ8-Q4X2RNLXXLZ9-low.png
 CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 10 mA to 1.5 A to 10 mA
Figure 8-5 Output Load Transient Response for VOUT = 0.65 V
GUID-20220315-SS0I-Z0QC-WKNH-V217BJ306WR8-low.png
 CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A, VIN = 3.9 V to 5.8 V to 3.9 V
Figure 8-7 Power-Up, Power-Down for VOUT = 0.65 V
GUID-20220315-SS0I-51HL-3TPZ-3KWNWSGK6KZ4-low.png
 CIN = COUT = 10 μF, CBIAS = 1 μF, IOUT = 1.5 A, VIN = 0.95 V to 6 V to 0.95 V
Figure 8-4 VIN Line Transient for VOUT = 0.65 V
GUID-2848BD8B-2D2A-49D1-B586-89F5601EBFA1-low.gifFigure 8-6 Turn-On Response