JAJSM31 May   2022 TPS7A74

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Global Undervoltage Lockout (UVLO) Circuit
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimating Junction Temperature
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.2 Sequencing Requirements

VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the soft-start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable for most applications, as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster than the set soft-start ramp rate.

There are several different start-up responses that are possible, but not typical:

  • If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply minus the dropout voltage until reaching the set output voltage
  • If EN is connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS
  • If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN
  • If the soft-start time has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft-start capacitor

Figure 7-3 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and VBIAS are present.

GUID-20220316-SS0I-M7HQ-NPP0-QHMK2NDNBKML-low.gif Figure 7-3 Soft-Start Delay Using an RC Circuit to Enable the Device