JAJSM31 May   2022 TPS7A74

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Global Undervoltage Lockout (UVLO) Circuit
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Estimating Junction Temperature
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 10 nF, IOUT = 10 mA, VBIAS = 5.0 V (4), and TJ = –40°C to 125°C, (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal reference (adj.) 0.641 0.65 0.659 V
Output accuracy (1)(5)(6) 2.97 V ≤ VBIAS ≤ 6 V, 0 mA ≤ IOUT ≤ 1.5 A –1.5 ±0.5 1.5 %
Line regulation (VBIAS) Max(2.7 V, VOUT + 1.6 V) ≤ VBIAS ≤ 6 V 0.2 0.32 %/V
Line regulation (VIN) VOUT(nom) + 0.15 V ≤ VIN ≤ 6 V 0.01 0.05 %/V
Load regulation 0 mA ≤ IOUT ≤ 1.5 A 0.33 %/A
VDO(IN) VIN dropout voltage(2) IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 2.8 V(3) 150 180 mV
VDO(BIAS) VBIAS dropout voltage(2) IOUT = 1.5 A, VIN = VBIAS 1.1 1.3 V
ICL Output current limit VOUT = 80% × VOUT(nom) 2 2.7 3.3 A
IBIAS BIAS pin current IOUT = 10 mA 0.25 0.33 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V, VIN = 6 V, VBIAS = 6 V 1 55 µA
IFB Feedback pin current –1 0.15 1 µA
VBIAS(UVLO) Bias rail UVLO rising threshold 1.04 1.4 1.65 V
VBIAS(UVLO), HYST Bias rail UVLO hysteresis 0.02 0.06 0.07 V
VIN(UVLO), rising In rail UVLO rising threshold 0.39 0.455 0.5 V
VIN(UVLO), falling In rail UVLO falling threshold 0.21 0.26 0.3 V
tSTR Minimum start-up time RLOAD for IOUT = 1.0 A, CSS = open 55 310 µs
ISS Soft-start charging current VSS = 0 V 8 17 31 µA
VSS Soft-start pin disable voltage VEN = 0 V 0 50 mV
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 55 mV
VEN(dg) Enable pin deglitch time 20 µs
IEN Enable pin current VEN = 5 V 0.1 0.2 µA
RPULLDOWN(OUT) VBIAS = 5 V, VEN = 0 V 0.6 1 kΩ
RPULLDOWN(FB) VBIAS = 5 V, VEN = 0 V 120 Ω
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 ℃
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.65 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted.
(4) VBIAS = VDO_MAX(BIAS) + VOUT for VOUT ≥ 3.4 V
(5) The device is not tested under conditions where VIN > VOUT + 1.65 V and IOUT = 1.5 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.
(6) The device is not tested under conditions where VIN > VOUT + 1.65 V and IOUT = 1.5 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.