JAJSH18A March   2019  – September 2019 TPS7A78

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハーフブリッジ構成の標準的な回路図
      2.      フルブリッジ構成の標準的な回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active Bridge Control
      2. 8.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 8.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 8.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 8.3.5 Dropout Voltage Regulation
      6. 8.3.6 Current Limit
      7. 8.3.7 Programmable Power-Fail Detection
      8. 8.3.8 Power-Good (PG) Detection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Dropout Mode
      3. 8.4.3 Disabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended Capacitor Types
      2. 9.1.2 Input and Output Capacitors Requirements
      3. 9.1.3 Startup Behavior
      4. 9.1.4 Load Transient
      5. 9.1.5 Standby Power and Output Efficiency
      6. 9.1.6 Reverse Current
      7. 9.1.7 Switched-Capacitor Stage Output Impedance
      8. 9.1.8 Power Dissipation (PD)
      9. 9.1.9 Estimating Junction Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculating the Cap-Drop Capacitor CS
          1. 9.2.2.1.1 CS Calculations for the Typical Design
        2. 9.2.2.2 Calculating the Surge Resistor RS
          1. 9.2.2.2.1 RS Calculations for the Typical Design
        3. 9.2.2.3 Checking for the Device Maximum ISHUNT Current
          1. 9.2.2.3.1 ISHUNT Calculations for the Typical Design
        4. 9.2.2.4 Calculating the Bulk Capacitor CSCIN
          1. 9.2.2.4.1 CSCIN Calculations for the Typical Design
        5. 9.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. 9.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design
        6. 9.2.2.6 Summary of the Typical Application Design Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SIMPLIS モデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VSCIN(1) = 4 (VLDO_OUT (nom) + 0.6 V) + 1 V or 17 V (whichever is greater), CSCIN = 10 µF, CS1 = 1.0 µF, CS2 = 2.2 µF , CLDO_IN = 10 µF, CLDO_OUT = 1.0 µF, and IOUT = 1 mA (unless otherwise noted);typical values are at TJ = 25°C(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO_SCIN UVLO_SCIN threshold rising VSCIN rising, VLDO_OUT(nom) ≤ 3.4 V  17 V
VUVLO_LDO_IN UVLO_LDO_IN threshold rising VSCIN rising 3.9 V
UVLO_LDO_IN threshold falling VSCIN falling 3.5 V
ΔVLDO_OUT(ΔIOUT) Load regulation 0 mA ≤ IOUT  ≤ 120 mA 0.21 mV/mA
VLDO_OUT Output voltage accuracy VSCIN(1)(3) = 4 (VLDO_OUT (nom) + 0.6 V) + 3 V,                                           0 mA ≤ IOUT  ≤ 120 mA  –2 1 2 %
ICL Output current limit VLDO_OUT = 0.9 x VLDO_OUT(nom) 145 215 300 mA
IDD_SCIN SCIN pin quiescent current VLDO_OUT(nom) = 3.3 V, IOUT = 0 mA, no R3, R4 280 µA
VRipple Output voltage ripple VAC = 120 V, 60 Hz, FB, CS = 1.0 µF, CSCIN = 180 µF, VLDO_OUT(nom) = 5 V, IOUT = 10 mA,                                                                                               scope BW = 10 MHz 3 mV
VIT(PFD,RISING) PFD pin rising threshold VPFD rising, R4 = 100 kΩ 1.24 1.42 V
VIT(PFD,FALLING) PFD pin falling threshold VPFD falling, R4 = 100 kΩ 1.17 1.25
VHYS(PFD) PFD pin hysteresis 110 mV
VIT(PG,RISING) PG pin rising threshold R3 = 100 kΩ, VSCIN rising 90.16 92 93.84 %VLDO_OUT
VIT(PG,FALLING) PG pin falling threshold R3 = 100 kΩ 88.5 90 91.5
VHYS(PG) PG pin hysteresis 2
VOL(PF),(PG) PF and PG pins low-level ouput voltage  IPF,PG = 500 µA 0.2 V
ILKG(PF),(PG) PF and PG pins open-drain leakage current VPF,PG = 5 V 50 nA
TSD(Shutdown) Thermal shutdown temperature Shutdown, temperature increasing 162 ℃
TSD(Reset) Thermal shutdown reset temperature Reset, temperature decreasing 135
(1) For VLDO_OUT > 4.4 V, VSCIN is limited to 24 V for testing purposes only.
(2) Electrcial characterestic data tested in DC supply mode equivalent to VSCIN voltage under AC supply mode.
(3) VSCIN ≥ 19 V.