JAJSDP9A August   2017  – September 2017 TPS7A88-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft-Start (NR/SSx)
        2. 7.3.2.2 Sequencing
          1. 7.3.2.2.1 Enable (ENx)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLOx) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PGx)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICLx)
        2. 7.3.3.2 Thermal Protection (Tsdx)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Setting the Output Voltage (Adjustable Operation)
        2. 8.1.1.2 Capacitor Recommendations
        3. 8.1.1.3 Input and Output Capacitor (CINx and COUTx)
        4. 8.1.1.4 Feedforward Capacitor (CFFx)
        5. 8.1.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SSx)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Circuit Soft-Start Control (NR/SSx)
          1. 8.1.2.1.1 In-Rush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLOx) Control
        3. 8.1.2.3 Power-Good (PGx) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.3.3 Output Voltage Noise
        4. 8.1.3.4 Optimizing Noise and PSRR
          1. 8.1.3.4.1 Charge Pump Noise
        5. 8.1.3.5 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUTx)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 8.1.5 Reverse Current Protection
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
        2. 11.1.1.2 SPICEモデル
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RTJ|20
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RTJ Package
20-Pin WQFN With Exposed Thermal Pad
Top View
TPS7A88-Q1 SBVS289_QFN_pinout.gif

Pin Functions

PIN DESCRIPTION
NAME NO. I/O
EN1 20 I Enable pin for each channel. These pins turn the regulator on and off. If VENx(1) ≥ VIH(ENx), then the regulator is enabled. If VENx ≤ VIL(ENx), then the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used.
EN2 6
FB1 16 I Feedback pins connected to the error amplifier. Although not required, a TI recommends a 10-nF feedforward capacitor from FBx to OUTx (as close as possible to the device) to maximize AC performance. The use of a feedforward capacitor can disrupt PGx (power good) functionality. See Feedforward Capacitor (CFFx) and Setting the Output Voltage (Adjustable Operation) for more details.
FB2 10
GND 3, 13 — Ground pins. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
IN1 1, 2 I Input supply pins for LDO 1. An input capacitor with a value of 10 µF or larger (5 µF or greater of effective capacitance) is required. Place the input capacitor as close as possible to the input.
IN2 4, 5 I Input supply pins for LDO 2. An input capacitor with a value of 10 µF or larger (5 µF or greater of effective capacitance) is required. Place the input capacitor as close as possible to the input.
NR/SS1 19 — Noise-reduction and soft-start pin for each channel. Connecting an external capacitor between this pin and ground reduces reference voltage noise and enables the soft-start function. Although not required, TI recommends connecting a capacitor with a value of 10 nF or larger from NR/SSx to GND (as close as possible to the pin) to maximize AC performance. See Noise-Reduction and Soft-Start Capacitor (CNR/SSx) for more details.
NR/SS2 7
OUT1 14, 15 O Regulated outputs for LDO 1. A ceramic capacitor with a value of 5 µF or larger (10 μF or greater of effective capacitance) from OUTx to ground is required for stability and must be placed as close as possible to the output. Minimize the impedance from the OUT1 pin to the load. See Input and Output Capacitor (CINx and COUTx) for more details.
OUT2 11, 12 O Regulated outputs for LDO 2. A ceramic capacitor with a value of 10 µF or larger (5 μF or greater of effective capacitance) from OUTx to ground is required for stability and must be placed as close as possible to the output. Minimize the impedance from the OUT2 pin to the load. See Input and Output Capacitor (CINx and COUTx) for more details.
PG1 17 O Open-drain power-good indicator pins for the LDO 1 and LDO 2 output voltages. A 10-kΩ to 100-kΩ external pullup resistor is required. These pins can be left floating or connected to GND if not used. The use of a feedforward capacitor can disrupt power-good functionality. See Feedforward Capacitor (CFFx) for more details.
PG2 9
SS_CTRL1 18 I Soft-start control pins for each channel. Connect these pins to GND or INx to allow normal or fast charging of the NR/SSx capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot.
SS_CTRL2 8
Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.