SBVS248A November   2015  – November 2015 TPS7A88

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Independent Dual-Channel LDO
      2. 7.3.2 Output Enable
      3. 7.3.3 Dropout Voltage (VDO)
      4. 7.3.4 Output Voltage Accuracy
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Internal Protection Circuitry
        1. 7.3.6.1 Undervoltage Lockout (UVLO)
        2. 7.3.6.2 Internal Current Limit (ICL)
        3. 7.3.6.3 Thermal Protection
      7. 7.3.7 Output Soft-Start Control
      8. 7.3.8 Power-Good Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Outputs
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (ENx) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SSx)
        3. 8.1.2.3 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CINx and COUTx)
        2. 8.1.3.2 Feed-Forward Capacitor (CFFx)
      4. 8.1.4 AC Performance
        1. 8.1.4.1 Power-Supply Ripple Rejection (PSRR)
        2. 8.1.4.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.4.3 Load-Step Transient Response
        4. 8.1.4.4 Noise
      5. 8.1.5 Power Dissipation (PD)
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance.

10.1.1 Board Layout

To maximize the ac performance of the TPS7A88, following the layout example illustrated in Figure 47 is recommended. This layout isolates the analog ground (AGND) from the noisy power ground. Components that must be connected to the quiet analog ground are the noise reduction capacitors (CNR/SSx) and the lower feedback resistors (R2, R4). These components must have a separate connection back to the power pad of the device. To minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite sides of the layout and only connect back to the device at opposite sides of the thermal pad. TI recommends connecting the GND pins directly to the thermal pad and not to any external plane.

To maximize the output voltage accuracy, the connection from each output voltage back to top output divider resistors (R1 and R3) must be made as close as possible to the load. This method of connecting the feedback trace eliminates the voltage drop from the device output to the load.

To improve thermal performance, a 3 × 3 thermal via array must connect the thermal pad to internal ground planes. A larger area for the internal ground planes improves the thermal performance and lowers the operating temperature of the device.

10.2 Layout Example

TPS7A88 layout_sbvs248.gif Figure 47. TPS7A88 Example Layout