SBVS248A November   2015  – November 2015 TPS7A88

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Independent Dual-Channel LDO
      2. 7.3.2 Output Enable
      3. 7.3.3 Dropout Voltage (VDO)
      4. 7.3.4 Output Voltage Accuracy
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Internal Protection Circuitry
        1. 7.3.6.1 Undervoltage Lockout (UVLO)
        2. 7.3.6.2 Internal Current Limit (ICL)
        3. 7.3.6.3 Thermal Protection
      7. 7.3.7 Output Soft-Start Control
      8. 7.3.8 Power-Good Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Outputs
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (ENx) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SSx)
        3. 8.1.2.3 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CINx and COUTx)
        2. 8.1.3.2 Feed-Forward Capacitor (CFFx)
      4. 8.1.4 AC Performance
        1. 8.1.4.1 Power-Supply Ripple Rejection (PSRR)
        2. 8.1.4.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.4.3 Load-Step Transient Response
        4. 8.1.4.4 Noise
      5. 8.1.5 Power Dissipation (PD)
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RTJ Package
4-mm × 4-mm 20-Pin WQFN
Top View
TPS7A88 po_RTJ_sbvs248.gif

Pin Functions

PIN DESCRIPTION
NAME NO. I/O
EN1 20 I Enable pin for each channel. These pins turn the regulator on and off. If VENx(1) ≥ VIH(ENx), the regulator is enabled. If VENx ≤ VIL(ENx), the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used.
EN2 6
FB1 16 I Feedback pin for each channel. These pins are the inputs to the control loop error amplifier and are used to set the output voltage of the device.
FB2 10
GND 3, 13 — Device GND. Connect both pins to the device thermal pad.
IN1 1, 2 I Input pin for LDO1. A 10 µF or greater input capacitor is required to assure robust operation.
IN2 4, 5 Input pin for LDO2. A 10 µF or greater input capacitor is required to assure robust operation.
NR/SS1 19 — Noise reduction pin for each channel. Connect these pins to an external capacitor to bypass the noise generated by the internal band-gap reference. The capacitor reduces the output RMS noise to very low levels and sets the output ramp rate to limit inrush current.
NR/SS2 7
OUT1 14, 15 O Regulated output 1. A 10 µF or greater capacitor must be connected from this pin to GND to assure stability.
OUT2 11, 12 Regulated output 2. A 10 µF or greater capacitor must be connected from this pin to GND to assure stability.
PG1 17 O Open-drain power-good indicator pins for the LDO1 and LDO2 output voltages. A 10-kΩ to 100-kΩ external pullup resistor is required. These pins can be left floating or connected to GND if not used.
PG2 9
SS_CTRL1 18 I Soft-start control pin for each channel. Connect these pins either to GND or INx to allow normal or fast charging of the NR/SSx capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot.
SS_CTRL2 8
Thermal pad — Connect the thermal pad to the printed circuit board (PCB) ground plane.
(1) Lowercase x indicates that the specification under consideration applies to both channel 1 and channel 2, one channel at a time.