JAJSN03A june   2022  – august 2023 TPS7B4255-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Tracker Output Voltage (VOUT)
        1. 7.3.1.1 Output Voltage Equal to the Reference Voltage
        2. 7.3.1.2 Output Voltage Less Than the Reference Voltage
      2. 7.3.2 Reverse Current Protection
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Thermal Protection
      5. 7.3.5 Current Limit
      6. 7.3.6 Output Short to Battery
      7. 7.3.7 Tracking Regulator With an Enable Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Operation With VIN < 3 V
      4. 7.4.4 Disable With ADJ/EN Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Dropout Voltage
      2. 8.1.2 Reverse Current
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Package Mounting
        2. 8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
        3. 8.4.1.3 Power Dissipation and Thermal Considerations
        4. 8.4.1.4 Thermal Performance Versus Copper Area
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Reverse Current Protection

The TPS7B4255-Q1 incorporates a back-to-back PMOS topology that protects the device from damage against a fault condition, resulting in VOUT being higher than VIN and the subsequent flow of reverse current. No damage occurs to the device if this fault condition occurs, provided the Absolute Maximum Ratings are not violated. This integrated protection feature eliminates the need for an external diode. The reverse current comparator typically responds to a reverse voltage condition in 1 μs, and along with the body diode of the blocking PMOS transistor, limits the reverse current to IREV.