JAJSC97C January   2015  – September 2018 TPS7B7701-Q1 , TPS7B7702-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fault Detection and Protection
      2. 7.3.2  Short-Circuit and Overcurrent Protection
      3. 7.3.3  Short-to-Battery and Reverse Current Detection
      4. 7.3.4  Thermal Shutdown
      5. 7.3.5  Integrated Reverse-Polarity Protection
      6. 7.3.6  Integrated Inductive Clamp
      7. 7.3.7  Undervoltage Lockout
      8. 7.3.8  Enable (EN, EN1, and EN2)
      9. 7.3.9  Internal Voltage Regulator (VCC)
      10. 7.3.10 Current Sense Multiplexing
      11. 7.3.11 Adjustable Output Voltage (FB, FB1, and FB2)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With IN < 4.5 V
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Current Sense Resistor Selection
        4. 8.2.2.4 Current-Limit Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at VI = 14 V and TJ = –40ºC to +150ºC (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VI Input voltage 4.5 40 V
IQ Quiescent current TPS7B7701-Q1: VI = 4.5 to 40 V, V(EN) ≥ 2 V, I(OUT) = 0.1 mA 0.6 1 mA
TPS7B7702-Q1: VI = 4.5 to 40 V, V(EN1) and V(EN2) ≥ 2 V, I(OUT1) and I(OUT2) = 0.1 mA 0.6 1
I(shutdown) Shutdown current TPS7B7701-Q1: EN = GND 5 µA
TPS7B7702-Q1: EN1 = EN2 = GND 5
Inom Operating current TPS7B7701-Q1: V(EN) ≥ 2 V, I(OUT) ≤ 300 mA, GND current 4.5 mA
TPS7B7702-Q1: V(EN1) and V(EN2) ≥ 2 V, I(OUT1) and I(OUT2) ≤ 300 mA, GND current 6
V(BG) Bandgap Reference voltage for FB –2% 1.233 2% V
V(UVLO) Undervoltage lockout falling Ramp IN down until the output turns off 4 V
Vhys Hysteresis 0.4 V
INPUT CONTROL PINS (EN, EN1, EN2, SENSE_EN, AND SENSE_SEL)
VIL Logic input low level For EN, EN1, EN2, SENSE_EN, and SENSE_SEL 0 0.7 V
VIH Logic input high level For EN, EN1, EN2, SENSE_EN, and SENSE_SEL 2 V
II(SENSE_EN) SENSE_EN input current V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V 10 µA
II(SENSE_SEL) SENSE_SEL input current V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V 10 µA
II(EN) Enable input current V(ENx) ≤ 40 V 10 µA
REGULATED OUTPUT (OUT, OUT1, AND OUT2)
VO Regulated output 40 V ≥ VI ≥ VO + 1.5 V and VI ≥ 4.5 V, IO = 1 to 300 mA(1) –2% 2%
ΔVO(ΔVI) Line regulation VI = VO + 1.5 V to 40 V and VI ≥ 6 V, IO = 10 mA, voltage variation on FB pin 10 mV
ΔVO(ΔIO) Load regulation IO = 1 mA to 200 mA, voltage variation on FB pin 20 mV
V(DROPOUT) Dropout voltage Measured between IN and OUTx, IO = 100 mA 500 mV
IO Output current VO in regulation 0 300 mA
PSRR Power supply ripple rejection(2) IO = 100 mA, CO = 2.2 µF, ƒ = 100 Hz 73 dB
CURRENT SENSE AND CURRENT-LIMIT
IO/ISENSE OUTx to SENSEx current ratio (IO / ISENSEx) VI = 4.5 V to 40 V, 5 mA ≤ IO ≤ 300 mA 198
OUTx to SENSEx current ratio accuracy IO = 100 to 300 mA –3% 3%
IO = 50 to 100 mA –5% 5%
IO = 10 to 50 mA –10% 10%
IO = 5 to 10 mA –20% 20%
IO/ILIM OUTx to LIMx current ratio (IO / ILIM) VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA 198
I(LIMx) Programmable current-limit accuracy(3) VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA –8% 8%
IL(LIMx) Internal current-limit LIMx shorted to GND 340 550 mA
Ilkg SENSE, SENSE1, SENSE2, LIM, LIM1, and LIM2 leakage current ENx = GND, TA = 25°C 2 µA
V(LIMx_th) Current-limit threshold voltage Voltage on the LIM, LIM1, and LIM2 pins when output current is limited 1.233 V
V(SENSEx_stb) Current-sense short-to-battery fault voltage When short-to-battery or reverse current conditions are detected 3.05 3.2 3.3 V
V(SENSEx_tsd) Current-sense thermal shutdown fault voltage When thermal shutdown is detected 2.7 2.85 3 V
V(SENSEx_cl) Current-sense current-limit fault voltage When current-limit conditions are detected 2.4 2.55 2.65 V
I(SENSEx_H) Current-sense fault condition current When short-to-battery, reverse current, thermal shutdown, or current-limit conditions are detected 3.3 mA
FAULT DETECTION
V(stb_th) Short-to-battery threshold V(OUTx) – VI, checked during turnon sequence –500 –55 110 mV
I(REV) Reverse current detection level Power FET on (SW or LDO mode) –100 –40 –1 mA
TSD Thermal shutdown Junction temperature 175 °C
TSD(hys) Thermal shutdown hysteresis 15 °C
INTERFACE CIRCUITRY
VOL ERR output low I(SINK) = 5 mA 0.4 V
Ilkg ERR open-drain leakage current ERR high impedance, 5-V external voltage is applied at ERR 1 µA
R(OUTx-off) OUT pulldown resistor(2) ENx = GND 50 kΩ
IR(lkg) Reverse leakage current –40 V < VI < 0 V, reverse current to IN 0.6 mA
VCC Internal voltage regulator VI = 5.5 to 40 V, ICC = 0 mA 4.25 4.5 4.75 V
ICC(lim) Internal voltage-regulator current-limit 15 70 mA
(1) External feedback resistor is not considered.
(2) Design information; specified by design, not production tested.
(3) The current-limit accuracy is maintained when the current limit is set between 50 mA and 300 mA, and it includes the deviation of the current-limit threshold voltage V(LIMx_th).