JAJSVD1 September   2024 TPS7C84-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reverse Current
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended Capacitor Types
          1. 7.2.1.1.1 Recommended Capacitors
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Feedback Resistor Selection
        2. 7.2.2.2 Feedforward Capacitor
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 D Package,8-Pin SOIC(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
EN 7 I Enable pin. The device is disabled when the enable pin becomes lower than the enable logic input low level (VIL). To make sure the device is enabled, drive the EN pin above the logic high level (VIH). Do not leave this pin floating because this pin is high impedance. If this pin is left floating, the pin state becomes undefined and the device potentially enables or disables.
FB/NC 2 I This pin is a feedback pin when using an external resistor divider or an NC pin when using the device with a fixed output voltage. When using the adjustable device, connect this pin through a resistor divider to the output for the device to function. See the Feedback Resistor Selection section for more information. If using a fixed output, leave this pin floating or connected to GND.
GND 5 — Ground
IN 8 I Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground. See the Recommended Operating Conditions table and the Input and Output Capacitor Requirements section. Place the input capacitor as close to the input of the device as possible.
NC 3, 4 — No internal connection. Leave this pin floating or tied to GND for best thermal performance.
OUT 1 O Regulated output voltage pin. A capacitor is required from OUT to GND for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to GND(2). Place the output capacitor as close to the device output as possible. See the Input and Output Capacitor Requirements section for more details.
PG 6 O Active-high, open-drain power-good output. This pin goes low when VOUT drops by 6% of the nominal value.
The power-good feature is functional when the device is enabled (VEN > VIH).
(1) I = input; O = output.
(2) Make sure the nominal output capacitance is greater than 1μF. Throughout this document, the nominal derating on these capacitors is 50%. Verify that the effective capacitance at the pin is greater than 1μF.