JAJSVD1 September 2024 TPS7C84-Q1
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOUT | Output voltage accuracy | VIN = [VOUT(NOM) + 1V] to 40V, IOUT = 100µA to 150mA | 25°C | –0.5 | 0.5 | % | |
–40°C to 150°C | –1 | 1 | |||||
ΔVOUT(ΔVIN) | Line regulation | VIN = [VOUT(NOM) + 1V] to 40V | –40°C to 150°C | 0.2 | %/V | ||
ΔVOUT(ΔIOUT) | Load regulation | IOUT = 100 µA to 150mA | 0.2 | % | |||
VDO | Dropout voltage | VIN = 2.1V, IOUT = 150mA | 480 | 900 | mV | ||
VIN = 3.5V, IOUT = 150mA | 450 | 600 | |||||
VIN=VOUT= 3.3V, IOUT = 150mA | 620 | ||||||
VIN=VOUT= 5V, IOUT = 150mA | 550 | ||||||
IQ | Quiescent current | IOUT = 100µA | 50 | 68 | µA | ||
IOUT = 150mA | 3.2 | mA | |||||
ISHUTDOWN | Shutdown supply current (IGND) | VEN ≤ 0.7V, VIN ≤ 40V, VOUT = 0V | 25°C | 4 | 6 | µA | |
–40°C to 150°C | 7.5 | ||||||
UVLO | UVLO VIN rising | IOUT = 100µA | –40°C to 150°C | 1.8 | 1.9 | 2.0 | V |
UVLO VIN falling | IOUT = 100µA | 1.7 | 1.8 | 1.9 | |||
Hysteresis | IOUT = 100µA | 100 | mV | ||||
ICL | Current limit | VOUT = 0V | 165 | 225 | 280 | mA | |
Vn | Output noise (RMS), 10Hz to 100KHz |
COUT = 1µF (5V only) | 25°C | 265 | µV | ||
PSRR | Power supply ripple rejection | VIN - VOUT = 1V, frequency = 100Hz, IOUT = 5mA | 25°C | 80 | dB | ||
IFB | FEEDBACK bias current | 25°C | 5 | 10 | nA | ||
–40°C to 150°C | 15 | ||||||
VPG(OL) | PG pin low level output voltage | VIN ≥ 2V, IOL = 400μA | 25°C | 180 | 250 | mV | |
–40°C to 150°C | 350 | ||||||
VPG(TH,RISING) | VOUT rising | –40°C to 150°C | 97 | %VOUT | |||
VPG(TH,FALLING) | VOUT falling | 92 | |||||
VPG(HYST) | Hysteresis | 25°C | 2 | ||||
VIL | Enable logic input low level | Low (regulator OFF) | –40°C to 150°C | 0.7 | V | ||
VIH | Enable logic input high level | High (regulator ON) | 1.9 | ||||
IEN | EN pin current | VEN = 40V | –40°C to 150°C | 1 | µA |