SLVSH48A May   2024  – September 2024 TPS7H1121-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspections
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Output Voltage (Feedback Circuit)
      2. 8.3.2  Enable
      3. 8.3.3  Dropout Voltage VDO
      4. 8.3.4  Output Voltage Accuracy
      5. 8.3.5  Output Noise
      6. 8.3.6  Power Supply Rejection Ratio (PSRR)
      7. 8.3.7  Soft Start
      8. 8.3.8  Power Good (PG)
      9. 8.3.9  Stability
        1. 8.3.9.1 Stability
        2. 8.3.9.2 STAB Pin
      10. 8.3.10 Programmable Current Limit
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable / Disable
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Configuration
        2. 9.2.2.2 Output Voltage Accuracy
        3. 9.2.2.3 Enable Threshold
        4. 9.2.2.4 Soft Start Capacitor
        5. 9.2.2.5 Programmable Current Limit Resistor
        6. 9.2.2.6 Characterization of Overcurrent Events that Exceed Thermal Limits
        7. 9.2.2.7 Power Good Pull Up Resistor
        8. 9.2.2.8 Capacitors
          1. 9.2.2.8.1 Hybrid Output Capacitor Network
        9. 9.2.2.9 Frequency Compensation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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発注情報

8.3.8 Power Good (PG)

Power Good terminal is an open-drain connection and can be used to sequence multiple LDOs. The PG terminal will be pulled low until the output voltage reaches 95% (typ) of its final level. At that point, the PG pin will be pulled up through the external resistor divider. Since the PG pin is open drain, it can be pulled up to any voltage as long as it does not exceed the recommended maximum of 7V listed in Section 6.5.

TPS7H1121-SP Sequenced Power Good Figure 8-1 Sequenced Power Good