SLVSH48A May   2024  – September 2024 TPS7H1121-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspections
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Output Voltage (Feedback Circuit)
      2. 8.3.2  Enable
      3. 8.3.3  Dropout Voltage VDO
      4. 8.3.4  Output Voltage Accuracy
      5. 8.3.5  Output Noise
      6. 8.3.6  Power Supply Rejection Ratio (PSRR)
      7. 8.3.7  Soft Start
      8. 8.3.8  Power Good (PG)
      9. 8.3.9  Stability
        1. 8.3.9.1 Stability
        2. 8.3.9.2 STAB Pin
      10. 8.3.10 Programmable Current Limit
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable / Disable
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Configuration
        2. 9.2.2.2 Output Voltage Accuracy
        3. 9.2.2.3 Enable Threshold
        4. 9.2.2.4 Soft Start Capacitor
        5. 9.2.2.5 Programmable Current Limit Resistor
        6. 9.2.2.6 Characterization of Overcurrent Events that Exceed Thermal Limits
        7. 9.2.2.7 Power Good Pull Up Resistor
        8. 9.2.2.8 Capacitors
          1. 9.2.2.8.1 Hybrid Output Capacitor Network
        9. 9.2.2.9 Frequency Compensation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HFT|22
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

HFT Package PWP Package
22-Pin CFP 24-Pin HTSSOP
Top View Top View
TPS7H1121-SP TPS7H1121-SP
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME HFT (22) NO. PWP (24) NO.
EN 1 2 I Enable. Driving this terminal to logic high enables the device; driving the terminal to logic low disables the device. If enable functionality is not required, connect this pin to IN using a resistor divider network, see Section 8.3.2. Do not float this pin.
IN 2, 3, 4, 5, 6, 7 3, 4, 5, 6, 7, 8 I Input power. An input capacitor (nominally 10μF) near this pin is recommended.
SS 8 9 I/O Soft-start. A minimum 1nF capacitor is required to prevent excessive inrush currents.
GND 9, 13, 14 10, 14, 15 — Ground
CL 10 11 I Programmable current limit. A resistor to GND sets the over-current limit activation point. The range of resistor that can be used on the CL terminal to GND is 41.2kΩ to 442kΩ.
STAB 11 12 I/O Stability pin. This is an output from the internal OTA (operational transconductance) error amplifier to aid in measuring or optimizing the control loop. Standard compensation networks can be applied to the STAB (see Section 8.3.9.1); however, an output capacitance of 22μF to 220μF typically achieve high stability margins.
FB 12 13 I The output voltage feedback input through voltage dividers. See Section 8.3.1.
NC - 1, 24 — No connect. This pin is not internally connected. It is recommended to connect these pins to GND to prevent charge buildup; however, these pins can also be left open or tied to any voltage between GND and VIN.
VLDO 15 16 O Output of internal linear regulator, requires a 470nF capacitor connected to ground.
OUT 16, 17, 18, 19, 20, 21 17, 18, 19, 20, 21, 22 O Output power pin. The regulated output voltage. A single 47µF tantalum or tantalum polymer capacitor is recommended. Capacitance values between 22µF and 220µF are generally supported without additional compensation and wider ranges are supported with use of the STAB pin. See Section 9.2.2.8 for additional information.
PG 22 23 I/O Power good indicator. This is an open drain pin. Use a pull-up resistor or a resistor divider (to ensure pin voltage does not exceed 7V) to achieve desired logic level when tied to VOUT. It is recommend to pull down PG to ground if left unused, the PG pin can be left floating if necessary. When the output reaches 95% (typ) of the set output voltage the PG pin is asserted.
Thermal pad — Internally grounded. It is recommended to connect this metal thermal pad to a large ground plane for effective heat dissipation.
Metal lid Lid N/A — The lid is internally connected to the thermal pad and GND through the seal ring.