SLVSAS4J June   2013  – April 2017 TPS7H1201-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Power Good (PG)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable/Disable
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Stability
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Adjustable Output Voltage (Feedback Circuit)
        2. 8.2.2.2 PCL
        3. 8.2.2.3 High-Side Current Sense
        4. 8.2.2.4 Current Foldback
        5. 8.2.2.5 Transient Response
        6. 8.2.2.6 Current Sharing
        7. 8.2.2.7 Compensation
        8. 8.2.2.8 Output Noise
        9. 8.2.2.9 Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The TPS7H1201-HT is a 0.5-A, 1.5- to 7-V LDO linear regulator that uses PMOS pass element configuration.

It uses TI’s proprietary process to achieve low noise, high PSRR combined with high thermal performance in a 16-terminal ceramic flatpack package (HKS) or KGD (bare die) package.

A number of features are incorporated in the design to provide high reliability and system flexibility. Overload protection is incorporated in the design to make it viable for harsh environments.

A resistor connected from the PCL terminal to ground sets the current limit activation point. When current limit activation point is reached, output voltage drops while output load current is maintained at current limit point.

The device also has a current sense monitoring feature. A resistor connected from the CS terminal to VIN indicates voltage proportional to the output load current. PCL provides a detailed description of this feature.

To provide system flexibility for demanding current needs, the LDO can be configured in parallel operation as indicated in Figure 24. Current Sharing provides detailed parallel operation information.

An enable feature is incorporated in the design allowing the user to enable or disable the LDO. Power Good, an open-drain connection, indicates the status of the output voltage. These provide the customers' system flexibility in monitoring and controlling the LDO operation. When using the Enable function, VIN voltage must be > 3.5 V. For VIN from 1.5 to 7 V, TPS7H1201-HT can be disabled using the SS terminal as described in Enable/Disable.

7.2 Functional Block Diagram

TPS7H1201-HT fbd1_lvsas4.gif Figure 10. Block Diagram

7.3 Feature Description

7.3.1 Soft Start

Connecting a capacitor from the SS terminal to GND (CSS) slows down the output voltage ramp rate. The soft-start capacitor charges up to 1.2 V.

Equation 1. TPS7H1201-HT eq3_css_slvsas4.gif

where

  • tss = Soft-start time
  • Iss = 2.5 µA
  • VFB = VREF / 2 = 0.605 V

7.3.2 Power Good (PG)

Power Good terminal (9) is an open-drain connection and can be used to sequence multiple LDOs. Figure 11 shows typical connection for VIN > 3.5 V. The PG terminal will be pulled low until the output voltage reaches 90% of its maximum level. At that point, the PG pin will be pulled up. Since the PG pin is open drain, it can be pulled up to any voltage as long as it does not exceed the absolute max of 7.5 V listed in the table.

TPS7H1201-HT PG_sequencing_slvsas4.gif Figure 11. Sequencing LDOs with Power Good

NOTE

For PSpice models, WEBENCH, and mini-POL reference design, see the Tools & Software tab.

  1. PSpice average model (stability – bode plot)
  2. PSpice transient model (switching waveforms)
  3. WEBENCH design tool (www.ti.com/product/TPS7H1201-HT/toolssoftware)

7.4 Device Functional Modes

7.4.1 Enable/Disable

For VIN from 1.5 V to 7 V, TPS7H1201-HT can be disabled using the SS terminal. The minimum soft-start pulldown current is 10 μA, with soft start to ground voltage of 400 mV or lower. External voltage applied to the SS terminal must be limited to 1.2-V maximum. Removing the logic-low condition on soft start enables the device allowing the soft-start capacitor to get charged by the internal current source. Alternatively, for VIN > 3.5 V, the device can be disabled by pulling the enable terminal to logic low. In all other cases, the enable terminal should be connected to VIN.

TPS7H1201-HT Enable_Disable_slvsas4.gif Figure 12. Enable/Disable

The circuit shown in Figure 12 highlights the SS terminal 1 along with block diagram of internal circuitry. Circuitry in dashed outline is internal to the IC composed of PMOSFET current mirror. The PMOS current mirror sources current from the positive supply and external circuitry composed of Qext is used to sink current from SS terminal 1. As highlighted in the table, typical ISS = 2.5 μA and max ISS = 3.5 μA for TPS7H1101-SP. If ISS current is exceeded, such as sinking higher current in excess of max ISS, this disables the LDO. See the table for the external sink current from SS terminal necessary to disable the IC. Exceeding maximum external sink current does not damage the device.