The TPS7H3301-SP is specifically designed to power up the memory termination rail (as shown in Figure 8-5). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 8-6 for typical characteristics for a single memory cell.

Figure 8-5 Typical Application Diagram for DDR3 VTT DIMM/Module Using TPS7H3301-SP

Figure 8-6 DDR Physical Signal System SSTL Signaling

In Figure 8-6, when Q1 is on and Q2 is off:

• Current flows from VDDQ via the termination resistor to VTT.
• VTT sinks current.

In Figure 8-6, when Q2 is on and Q1 is off:

• Current flows from VTT via the termination resistor to GND.
• VTT sources current.

Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2. See Table 8-2 for detailed information and JEDEC relevant specifications.

VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both DC and AC conditions

The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.

The TPS7H3301-SP ensures the regulator output voltage to be:

VTTREF – 34 mV < VTT < VTTREF + 34 mV, for both DC and AC conditions and –3 A < I_VTT < 3 A

The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to DDR, DDR2, DDR3 and low-power DDR3/DDR4 applications (see Table 8-2 for detailed information). To meet the stability requirement, a minimum output capacitance of 470 μF is needed, combination of both tantalum and ceramic capacitors. Considering the actual tolerance on the MLCC capacitors, four or higher 4.7-μF ceramic capacitors in parallel with 3 × 150-µF low-ESR tantalum capacitor are sufficient to meet the above requirement. Higher ESR tantalum capacitors will require multiple tantalum capacitors in parallel with ceramic capacitors to meet system needs.

The TPS7H3301-SP is designed as a Gm-driven LDO. The voltage droop between the reference input and the output regulator is determined by the transconductance and output current of the device. The typical Gm is 250 S at 3 A and changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see Equation 1).

Equation 1.

where

• F_UGBW is the unity gain bandwidth
• Gm is transconductance
• C_OUT is the output capacitance

There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. To maintain stability, the zero location contributed by the ESR of the output capacitors should be greater than the –3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to prevent the gain peaking effect around the Gm –3-dB point because of the large ESL, the output capacitor, and parasitic inductance of the VTT/V_O trace.

Figure 8-7 shows the bode plot simulation for a typical DDR3 configuration of the TPS7H3301-SP, where:

• VDD/V_IN = 2.4 V
• V_VLDOIN = 1.5 V
• VTT/V_O = 0.75 V
• I_IO = 2 A
• 3 × 150-μF low-ESR tantalum capacitors (T530D157M010ATE005) in parallel with 4 × 4.7-µF ceramic capacitor
• ESR = 1.66 mΩ
• ESL = 800 pH

The unity-gain bandwidth is approximately 87.3 kHz and the phase margin is 82°. The 0-dB level is crossed, the gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.

Figure 8-7 Bode Plot for a Typical DDR3 Configuration

Figure 6-3 shows the load regulation and Figure 8-8 shows the transient response for a typical DDR3 configuration. When the regulator is subjected to worst case ±3-A load step. The current shown only represents the device sourcing 3 A due to location of current probe.

Figure 8-8 Transient Plot