SLVSCJ5C December   2015  – September 2024 TPS7H3301-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT/VO Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD/VIN Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VIN Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
  10.   Power Supply Recommendations
  11. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  12. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  13.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over full temperature range, TA = –55°C to 125°C, VDD/VIN = 3.3 V and 2.375 V (for VDD/VIN > VLDOIN), VLDOIN = 1.8 V, VDDQSNS = 1.8 V, VTTSNS = 0.9 V, EN = VDD/VIN, Standard DDR Application unless otherwise noted. All voltage values are with respect to the network ground (AGND) pin unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVDD/Vin Supply current EN = 3.3 V, no load 18 30 mA
IVDD(SDN) Shutdown current EN = 0 V, VDDQSNS = 0, no load 3 5 mA
EN = 0 V, VDDQSNS > 0.78 V, no load 6.5 8
IVLDOIN Supply current of VLDOIN EN = 3.3 V, no load 575 1200 μA
IVLDOIN(SDN) Shutdown current of VLDOIN EN = 0 V, no load 50 100 μA
INPUT CURRENT
IVDDQSNS Input current, VDDQSNS EN = 3.3 V 4 6 μA
VTT/VO OUTPUT
VTTSNS Output DC voltage, VTT/VO IVTT = 5 mA VDDQSNS = VLDOIN 2.5 V (DDR1) 1.219 1.25 1.276 V
VDDQSNS = VLDOIN 1.8 V (DDR2) 0.889 0.9 0.921
VDDQSNS = VLDOIN 1.5 V (DDR3) 0.743 0.75 0.769
VDDQSNS = VLDOIN 1.35 V (DDR3L) 0.668 0.67 0.691
VDDQSNS = VLDOIN 1.2 V (DDR4) 0.593 0.6 0.617
IVTT = -5 mA VDDQSNS = VLDOIN 2.5 V (DDR1) 1.22 1.25 1.272 V
VDDQSNS = VLDOIN 1.8 V (DDR2) 0.89 0.9 0.923
VDDQSNS = VLDOIN 1.5 V (DDR3) 0.744 0.75 0.767
VDDQSNS = VLDOIN 1.35 V (DDR3L) 0.669 0.675 0.691
VDDQSNS = VLDOIN 1.2 V (DDR4) 0.594 0.6 0.616
-1 A ≤ IVTT ≤1 A VDDQSNS = VLDOIN 2.5 V (DDR1) 1.219 1.26 1.301 V
VDDQSNS = VLDOIN 1.8 V (DDR2) 0.879 0.91 0.933
VDDQSNS = VLDOIN 1.5 V (DDR3) 0.734 0.76 0.781
VDDQSNS = VLDOIN 1.35 V (DDR3L) 0.655 0.69 0.708
VDDQSNS = VLDOIN 1.2 V (DDR4) 0.58 0.6 0.633
VDO

Dropout voltage,

VDO = VLDOIN - VTTREF.

VDO recorded when

VTTREF - VTT = 50 mV

 VDDQSNS = 2.5 V (DDR1) IVTT = 0.5 A 50 230 mV
IVTT = 1 A 101 300
IVTT = 2 A 209 400
VDDQSNS = 1.8 V (DDR2) IVTT = 0.5 A 54 230
IVTT = 1 A 108 300
IVTT = 2 A 228 400
VDDQSNS = 1.5 V (DDR3) IVTT = 0.5 A 52 230
IVTT = 1 A 104 300
IVTT = 2 A 216 400
VDDQSNS = 1.35 V (DDR3) IVTT = 0.5 A 50 230
IVTT = 1 A 102 300
IVTT = 2 A 212 400
VDDQSNS = 1.2 V (DDR4) IVTT = 0.5 A 50 230
IVTT = 1 A 102 300
IVTT = 2 A 210 400
VTT/VO(TOL) Output voltage tolerance to VTTREF IVTT/VO = –3 A, across VDD/VIN voltage range 12 25 34 mV
IVTT/VO = 3 A, across VDD/VIN voltage range –34 –25 –12
IVOSRCL VTT/VO source current limit Ramp output 0 A to 10 A, record current when VTT reaches lowest value 3.25 8 A
IVOSNCL VTT/VO/VTT sink current limit Ramp output 0 A to -10 A, record current when VTT reaches highest value 3.5 10 A
RDSCHRG Discharge impedance VDDQSNS = 0 V, VTT/VO = 0.3 V, EN = 0 V 18 25 Ω
POWER-GOOD COMPARATOR
VTH(PG) VTT/VO PGOOD threshold PGOOD window lower (falling) threshold with respect to VVTTREF –23.5% –20% –17.5%
PGOOD window upper (rising) threshold with respect to VVTTREF 17.5% 20% 23.5%
PGOOD hysteresis 5%
TPGSTUPDLY PGOOD start up delay Start up rising edge, VTTSNS within 15% of VVTTREF 2 ms
VPGOODLOW Output low voltage ISINK = 4 mA 0.4 V
TPBADDLY PGOOD bad delay VTTSNS is outside of the ±20% PGOOD window 1 μs
IPGOODLK Leakage current VTTSNS = VTTREF (PGOOD high impedance),
PGOOD = VDD/VIN + 0.2 V		 1 μA
VDDQSNS AND VTTREF OUTPUT
VVDDQSNS_UVLO VDDQSNS undervoltage lockout VDDQSNS rising 780 mV
VVDDQSNSUVHYS VDDQSNS undervoltage lockout hysteresis 20 mV
VVTTREF VTTREF voltage VDDQSNS / 2 V
VTTREF(load_reg) Load reg ΔVTTREF –10 mA < IVTTREF < 10 mA VDDQSNS = 2.5 V –15 15 mV
VDDQSNS = 1.8 V –15 15
VDDQSNS = 1.5 V –15 15
VDDQSNS = 1.35 V –15 15
VDDQSNS = 1.2 V –15 15
VTTREFaccuracy VTTREF voltage tolerance to VDDQSNS –10 mA < IVTTREF < 10 mA VDDQSNS = 2.5 V 49% 51%
VDDQSNS = 1.8 V 49% 51%
VDDQSNS = 1.5 V 49% 51.25%
VDDQSNS = 1.35 V 49% 51.5%
VDDQSNS = 1.2 V 49% 51.5%
–3 mA < IVTTREF < 3 mA VDDQSNS = 1.5 V 49% 51%
VDDQSNS = 1.35 V 49% 51%
VDDQSNS = 1.2 V 49% 51%
IVTTREFSRCL VVTTREF source current limit Sourcing current ramped from 0 A to 55 mA. Find when VTTREF drops to half of its original value. 10 40 mA
IVTTREFSNCCL VVTTREF sink current limit Sinking current ramped from 0 A to 16.5 mA. Find when VTTREF hits peak value. 12 15 mA
IVTTREFDIS VTTREF discharge current EN = 0 V, VDDQSNS = 0 V, VTTREF = 0.5 V 1.3 mA
UVLO/EN LOGIC THRESHOLD
VVINUVVIN UVLO threshold Wakeup 2.18 2.25 V
VVINUVVINHYS UVLO threshold hysteresis Hysteresis 50 mV
VENIH High-level input voltage Enable 1.7 V
VENIL Low-level input voltage Enable 0.3 V
VENYST Hysteresis voltage Enable 0.5 V
IENLEAK Logic input leakage current EN –1 1 μA
THERMAL SHUTDOWN
TSON Thermal shutdown threshold Shutdown temperature 210 °C
Hysteresis 12