The TPS7H3302 supports tracking startup of VDDQ and shutdown when EN is tied directly to the system bus and not used to turn on or turn off the device. During tracking startup, VTT follows VTTREF once VDDQSNS voltage is greater than 0.75 V. VDDQSNS incorporates a resistor divider network and a time constant of about 445 µs. The rise time of the VTT output is then a function of the rise time of VDDQSNS. If the VDDQSNS rise time is larger than 445 µs. Typically PGOOD is asserted 4 ms after VTT is within ±20% of VTTREF. During tracking shutdown, VTT falls following VTTREF until VTTREF reaches 0.37 V (typically). Once VTTREF falls below 0.37 V, the internal discharge MOSFETs are turned on and quickly discharge both VTTREF and VTT to GND. PGOOD is deasserted once VTT is beyond the ±20% range of VTTREF. Figure 8-4 shows the typical timing diagram for an application that uses tracking startup and shutdown.

There are no sequencing requirements between VDD and VLDOIN. If VLDOIN is applied first followed by VDD there is no issue. VDD UVLO protection monitors VDD voltage. When VDD is lower than UVLO threshold both VTT and VTTREF regulators are powered off.

Figure 8-4 Typical Timing Diagram of Tracking Startup and Shutdown