JAJSNN5 January   2022 TPS7H4003-SEP

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjust UVLO
      7. 7.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 7.3.7.1 Internal Oscillator Mode
        2. 7.3.7.2 External Synchronization Mode
        3. 7.3.7.3 Primary-Secondary Operation Mode
      8. 7.3.8  Soft-Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Sequencing
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Turn-On Behavior
      15. 7.3.15 Slope Compensation
        1. 7.3.15.1 Slope Compensation Requirements
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Output Schottky Diode
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Soft-Start Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 8.2.2.8 Output Voltage Feedback Resistor Selection
          1. 8.2.2.8.1 Minimum Output Voltage
        9. 8.2.2.9 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 DDW Package
44-Pin HTSSOP
(Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1, 2, 10, 35 GND — Return for control circuitry.
3, 42–44 NC I No connect.
4 EN I EN pin is internally pulled up allowing for the pin to be floated to enable the device.
5 RT I/O A resistor connected between RT and GND sets the switching frequency of the converter. The switching frequency range is 100 kHz to 1 MHz. When an external clock is used, RT must be selected such that the set switching frequency coincides with the frequency of the applied clock. Leaving this pin floating sets the internal switching frequency to 500 kHz and SYNC1 and SYNC2 become output clocks at 500 kHz, with SYNC1 aligned with the converter switching and SYNC2 90° out of phase.
6, 7 VIN I Input power for the control circuitry of the switching regulator.
8 SYNC1 I/O SYNC1 is an input when an external clock is provided. The frequency of the external clock should match the switching frequency that is set by the resistor between RT and GND. With an external clock applied, the converter switching action is 180° out of phase with the external clock. When RT is floating, SYNC1 serves as an output of a 500-kHz clock signal that is in phase with the converter switching action. SYNC1 can be used in combination with SYNC2 in order to connect up to four devices in parallel.
9 SYNC2 I/O SYNC2 is used for connecting multiple devices in parallel. For the primary device, with RT floating, SYNC2 outputs 500-kHz signal that is 90° out of phase with the SYNC1 output clock. For the secondary devices, in which RT is populated, SYNC2 is used to configure the phase of the input clock signal on SYNC1. When SYNC2 is connected to VIN, the internal clock of the secondary device is in phase with clock provided at SYNC1. When SYNC2 is connected to GND, the input clock signal at SYNC1 is internally inverted.
11–15 PVIN I Input power for the output stage of the switching regulator.
16–22 PGND — Return for low-side power MOSFET.
23–34 PH O Switch phase node.
36 PWRGD O Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown, or during soft-start.
37 RSC I/O A resistor to GND sets the desired slope compensation.
38 SS/TR I/O Soft-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
39 VSENSE I Inverting input of the gm error amplifier.
40 COMP I/O Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.
41 REFCAP O Required 470-nF external capacitor for internal reference.
PowerPAD™ — Used for heat sinking by soldering to GND copper on printed circuit board.