JAJSU64A April   2024  – August 2024 TPS7H4011-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Remote Sensing and Setting VOUT
        1. 8.3.3.1 Minimum Output Voltage
        2. 8.3.3.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Fault Input (FAULT)
      6. 8.3.6  Power Good (PWRGD)
      7. 8.3.7  Adjustable Switching Frequency and Synchronization
        1. 8.3.7.1 Internal Clock Mode
        2. 8.3.7.2 External Clock Mode
        3. 8.3.7.3 Primary-Secondary Synchronization
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Soft-Start (SS_TR)
        2. 8.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 8.3.8.3 Tracking and Sequencing
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 8.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 8.3.9.1.3 COMP Shutdown
          4. 8.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 Schottky Diode
      3. 9.2.3 Application Curve
      4. 9.2.4 Parallel Operation Compensation
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HLB|30
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TPS7H4011-SP HLB Package, 30-Pin CFP (Top View)Figure 5-1 HLB Package, 30-Pin CFP
(Top View)
TPS7H4011-SP DDW Package, 44-Pin HTSSOP (Top View)Figure 5-2 DDW Package, 44-Pin HTSSOP
(Top View)
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME CFP
(30)		 HTSSOP
(44)
GND 1 1, 2 — Ground. Return for control circuitry.
EN 2 3 I Enable. Driving this pin to logic high enables the device; driving the pin to logic low disables the device. A resistor divider from VIN to GND may be used to set the device turn-on level.
RT 3 4 I/O A resistor connected between RT and GND sets the switching frequency of the converter. The switching frequency range is 100kHz to 1MHz. If the device is configured to utilize an external clock, this pin may be left floating or a resistor may be used to provide a backup frequency if the external clock is lost.
VIN 4 5 I Input voltage. Power for the control circuitry of the switching regulator. It must be the same voltage as PVIN and is therefore recommended to externally connect VIN to PVIN.
LDOCAP 5 6 O Linear regulator output capacitor pin. A 1µF capacitor must be placed on this pin for the internal linear regulator. The output voltage, AVDD, is nominally 5V. Do not load this pin with any additional external circuitry (other than circuitry which is explicitly allowed and mentioned in the data sheet).
SYNCM 6 7 I Synchronization mode pin. Connect this pin to GND to switch at the RT programmed frequency and output synchronization signals on SYNC1 and SYNC2. Leave this pin disconnected to switch at the RT programmed frequency and not output signals on SYNC1 and SYNC2. Connect this pin to AVDD (LDOCAP output) to use an external input clock. See Section 8.3.7 for additional information.
SYNC1 7 8 I/O Synchronization pin 1. This pin is used as an output clock sync pin (to synchronize other devices or aid in device monitoring) or an input for an external clock. SYNC1 outputs a clock signal in phase with the TPS7H4011 switching frequency when SYNCM is grounded. SYNC1 is an external clock input to set the device switching frequency when SYNCM is connected to AVDD. SYNC1 is unused and may be left floating or grounded when SYNCM is disconnected. See Section 8.3.7 for additional information.
SYNC2 8 9 I/O Synchronization pin 2. This pin is used as an output clock sync pin (to synchronize other devices or aid in device monitoring) or a device configuration pin when an external clock is used on SYNC1. SYNC2 outputs a clock signal 90° out of phase with the TPS7H4011 switching frequency when SYNCM is grounded.
SYNC2 determines whether the input clock on SYNC1 is in phase or 180° out of phase with the TPS7H4011 switching frequency when SYNCM is connected to AVDD. If SYNC2 is connected to GND, the device switches 180° out of phase with the SYNC1 input frequency. If SYNC2 is connected to AVDD (LDOCAP output), the device switches in phase with the SYNC1 input frequency. SYNC2 is unused and may be left floating or grounded when SYNCM is disconnected. See Section 8.3.7 for additional information.
PVIN 9–11 11–15 I Power stage input voltage. Power for the output stage of the switching regulator.
PGND 12–15 16–22 — Power stage ground. Return for low-side power MOSFET. Connect to GND on the PCB.
SW 16–21 23–34 O Switching node pins. Switch node output. It is recommended to connect a Schottky diode from SW to PGND.
PWRGD 22 36 O Power Good pin. This is an open-drain pin. Use a pull-up resistor to pull this pin up to VOUT (assuming VOUT is under 7V) or the desired logic level. PWRGD is asserted when the output voltage is within 5% (typ) of its programmed value. PWRGD is deasserted when the output voltages is outside 8% (typ) of its programmed value or when there is a fault condition (such as thermal shutdown).
FAULT 23 37 I Fault pin. This pin is provided for flexible fault management (such as overvoltage or an external fault input). When the 0.6V (typ) rising threshold on this pin is exceeded, the device will stop switching. When the 0.5V (typ) falling threshold on this pin is met, the device will resume switching after a 31 cycle (typ) delay. This pin is internally pulled-down and if unused may be grounded or left disconnected. See Section 8.3.5 for additional information.
ILIM 24 38 I Current limit pin. The voltage on this pin as a percentage of AVDD (LDOCAP output) determines which of four current limits will be selected for the FET high side current limit. Connect this pin to AVDD for an 18.3A (typ) current limit. Use a resistor divider from AVDD to GND of RILIM_TOP = 49.9kΩ and RILIM_BOT = 100kΩ (this sets ILIM to ~66% of AVDD) for a 13.4A (typ) current limit. Use a resistor divider of RILIM_TOP = 100kΩ and RILIM_BOT = 49.9kΩ (this sets ILIM to ~33% of AVDD) for a 9A (typ) current limit. Connect this pin to GND for a 5.6A (typ) current limit.
RSC 25 39 I/O Slope compensation pin. A resistor from RSC to GND sets the desired slope compensation.
SS_TR 26 40 I/O Soft-start and tracking. An external capacitor connected between this pin and VSNS- slows down the rise time of the internal reference. It can also be used for tracking and sequencing.
VSNS- 27 41 I Negative voltage sense. Connect this to the remote ground for differential sensing. If differential sensing is not desired, connect this pin to local ground. See Section 8.3.3 for additional information.
VSNS+ 28 42 I Positive voltage sense. This is the feedback pin that will be set to a nominal 0.6V by selecting the appropriate resistor divider network. See Section 8.3.3 for additional information.
COMP 29 43 I/O Compensation pin. This is the operational transconductance (OTA) error amplifier output and input to the switch current comparator. Connect frequency compensation to this pin.
REFCAP 30 44 O Reference capacitor pin. A 470nF external capacitor is required for the internal bandgap reference. The voltage, VBG, is nominally 1.2V. Do not connect external circuitry to this pin.
NC N/A 10, 35 — No connect. These pins are not internally connected. It is recommended to connect these pins to GND to prevent charge buildup; however, these pins can also be left open or tied to any voltage between GND and VIN.
THERMAL PAD 31 45 — Thermal pad internally connected to GND. Connect to a large ground plane for thermal dissipation. While it is recommended to electrically connect to GND or PGND; it may be left electrically disconnected if desired.
PGND PAD 32 N/A — Power ground pad. This pad is utilized to provide a low electrical resistance path for the low-side power MOSFET to PGND. It must be connected to the PGND pins.
SW PAD 33 N/A O Switch node. This pad is utilized to provide a low electrical resistance path for the switching current. It must be connected to the SW pins.
Metal lid Lid N/A — Internally connected to GND.
(1) I = Input, O = Output, I/O = Input or Output, — = Other