JAJSU64A April   2024  – August 2024 TPS7H4011-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Remote Sensing and Setting VOUT
        1. 8.3.3.1 Minimum Output Voltage
        2. 8.3.3.2 Maximum Output Voltage
      4. 8.3.4  Enable
      5. 8.3.5  Fault Input (FAULT)
      6. 8.3.6  Power Good (PWRGD)
      7. 8.3.7  Adjustable Switching Frequency and Synchronization
        1. 8.3.7.1 Internal Clock Mode
        2. 8.3.7.2 External Clock Mode
        3. 8.3.7.3 Primary-Secondary Synchronization
      8. 8.3.8  Turn-On Behavior
        1. 8.3.8.1 Soft-Start (SS_TR)
        2. 8.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 8.3.8.3 Tracking and Sequencing
      9. 8.3.9  Protection Modes
        1. 8.3.9.1 Overcurrent Protection
          1. 8.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 8.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 8.3.9.1.3 COMP Shutdown
          4. 8.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 8.3.9.2 Output Overvoltage Protection (OVP)
        3. 8.3.9.3 Thermal Shutdown
      10. 8.3.10 Error Amplifier and Loop Response
        1. 8.3.10.1 Error Amplifier
        2. 8.3.10.2 Power Stage Transconductance
        3. 8.3.10.3 Slope Compensation
        4. 8.3.10.4 Frequency Compensation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Operating Frequency
        2. 9.2.2.2  Output Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Input Capacitor Selection
        5. 9.2.2.5  Soft-Start Capacitor Selection
        6. 9.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 9.2.2.7  Output Voltage Feedback Resistor Selection
        8. 9.2.2.8  Output Voltage Accuracy
        9. 9.2.2.9  Slope Compensation Requirements
        10. 9.2.2.10 Compensation Component Selection
        11. 9.2.2.11 Schottky Diode
      3. 9.2.3 Application Curve
      4. 9.2.4 Parallel Operation Compensation
      5. 9.2.5 Inverting Buck-Boost
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HLB|30
サーマルパッド・メカニカル・データ
発注情報

9.2.4 Parallel Operation Compensation

The TPS7H4011 can be paralleled in a primary-secondary mode to achieve increased output current as described in Section 8.3.7.3. The current through each of the n paralleled devices will nominally be 1/n. The TPS7H4011 is designed to inherently support paralleling up to four devices with out of phase operation to reduce ripple.

In parallel mode, the current mismatch due to error amplifier gmEA differences are minimized since the output of the error amplifiers are all electrically connected by connection of the COMP pins. Therefore, the current mismatch is dominated by the mismatch of the individual power stage gmPS values. This parameter is specified in the Electrical Characteristics table for an IOUT of 12A and an IOUT of 9A across temperature. If it is assumed the n parallel devices will operate at a similar temperature, the gmPS mismatch can be considered across each individual temperature band, thus minimizing worst case error estimates.

There are two approaches to compensate the TPS7H4011 when in parallel mode. The first is to compensate the primary device and connect all COMP pins together. To do this, follow Section 9.2.2.10 but be sure to use the total output capacitance, COUT, and total output current, IOUT, of the complete system (not just the output current or output capacitance of a single device). Adjust the RCOMP calculation used in step #3 to Equation 28, where n is the number of paralleled devices.

Equation 28. R C O M P = 1 n 2 × A V M g m E A × V O U T V R E F

Alternatively, each device may be individually compensated following the steps described in Section 9.2.2.10. In this case, the output capacitance, COUT, and output current, IOUT, should be the individual COUT and IOUT of each device (in other words, scale the total COUT and IOUT by 1/n). The COMP pins should still be tied together but there is no need to change the equation in step #3. The disadvantage of this approach is increased component count, but the advantage is that it may reduce the noise that gets injected into the COMP pin due to the physically close compensation components near each device.

Other items to follow include:

  • Only a single feedback network is connected to the VSNS+ and VSNS- network of the primary device. Therefore, all VSNS+ nodes must be connected and all VSNS- nodes must be connected.
  • An individual soft-start capacitor is required per device.
  • Only a single enable signal (or resistor divider) is needed. Connect all EN pins together.
  • Only a single FAULT signal (or resistor divider) is needed. Connect all FAULT pins together.
  • Connect all PGOOD pins together and use a single pull-up resistor in order to have a wired-OR power good signal.
  • Connect the SYNC pins as described in Figure 8-10 through Figure 8-13 depending on the number of devices paralleled. It may also be possible to synchronize to an external clock if desired.