The TPS7H60x5 has undervoltage lockout (UVLO) on BP5L, BP7L, BP5H, BOOT, and VIN. When the output voltage on any of the low-side linear regulators or VIN falls below the UVLO threshold (4.05V for the BP5L linear regulator, 6.2V for the BP7L linear regulator, and 8.1V for VIN), the PWM inputs are ignored to prevent the GaN FETs from partial turn-on. In this scenario, the UVLO actively pulls LO and HO low. When the low-side regulators and VIN are each above the respective UVLO threshold but one of the high-side UVLOs is triggered (4.05V for BP5H and/or 6.65V for BOOT), then only HO is pulled low.

The gate driver also has a power good (PGOOD) pin, which indicates when any of the low-side linear regulators have entered undervoltage lockout. The pin enters the logic-high state when all low-side regulators and VIN each have surpassed the respective rising UVLO threshold. The pin goes, or remains, logic-low if any one of these linear regulators or VIN falls below the corresponding falling UVLO threshold. The PGOOD pin has an internal pull-down resistance of 1MΩ when the pin is in the logic-high state. A pull-up of 10kΩ connected from PGOOD to BP5L is recommended.