SNOSDH4 June   2024 TPS7H6005-SEP , TPS7H6015-SEP , TPS7H6025-SEP

ADVMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Device Options Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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発注情報

Overview

The TPS7H60x5 series of radiation-hardness-assured (RHA) half-bridge gate drivers are intended for use with enhancement mode GaN FETs. The series consists of the TPS7H6005 (200V driver), TPS7H6015 (60V driver), and the TPS7H6025 (22V driver). Each driver in the series has a 56-pin HTSSOP package and is available in both QMLP and SEP device grades. The drivers can be utilized in high frequency, high efficiency GaN based power converter designs. Each driver is designed to have a propagation delay of 30ns (typical) as well as 5.5ns (typical) high-side to low-side delay matching.

The drivers contain high-side and low-side internal linear regulators. These ensure that the gate voltages are maintained at 5V in order to prevent any damage of the GaN devices that are being driven. Split outputs on the high-side and low-side drivers provide the user the flexibility to independently adjust the turn-on and turn-off times of the GaN FETs. An external bootstrap diode is required for the gate drivers and as such, the user has the ability to optimize the diode based on the application. The drivers contain an internal switch in series with the bootstrap diode that can be used to prevent overcharging of the bootstrap capacitor and decreases reverse recovery losses in the diode.

The gate drivers have two modes of operation: PWM mode and independent input mode (IIM). The dual mode operation allows for each gate driver to be used with a wide number of PWM controllers to enable both synchronous rectifier control and GaN FET compatibility. The user also has the option to enable input interlock protection in IIM, allowing for anti-shoot through protection in synchronous buck and half-bridge topologies. This protection can also be disabled in IIM if desired, which allows the drivers to be utilized in two-switch forward converters and dual single ended applications.