SNOSDH4 June   2024 TPS7H6005-SEP , TPS7H6015-SEP , TPS7H6025-SEP

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Quality Conformance Inspection
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  Inputs and Outputs
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitors
        2. 9.2.2.2 Bootstrap Diode
        3. 9.2.2.3 BP5x Overshoot and Undershoot
        4. 9.2.2.4 Gate Resistor
        5. 9.2.2.5 Dead Time Resistor
        6. 9.2.2.6 Gate Driver Losses
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCA|56
サーマルパッド・メカニカル・データ
発注情報

7.6 Switching Characteristics

Specifications are over ambient temperature operating range TA = –55°C to 125°C, VIN = 10V to 14V, VBP5L = VBP5H = 5V, and no load on LOH, LOL, HOH, and HOL (unless otherwise noted).
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
tLPHL LO turnoff propagation delay MODE = PWM PWM rising to LOL falling 9, 10, 11 30 48 ns
MODE = IIM LI falling to LOL falling 9, 10, 11 27 38
tLPLH LO turnon propagation delay MODE = IIM LI rising to LOH rising 9, 10, 11 24 38 ns
tHPHL HO turnoff propagation delay MODE = PWM PWM falling to HOL falling 9, 10, 11 35 50 ns
MODE = IIM HI falling to HOL falling 9, 10, 11 30 40
tHPLH HO turnon propagation delay MODE = IIM HI rising to HOH rising 9, 10, 11 26 40 ns
tMON Delay matching LO on and HO off(3) MODE = IIM 9, 10, 11 5.5 12 ns
tMOFF Delay matching LO off and HO on(3) MODE = IIM 9, 10, 11 1.5 4 ns
tHRC HO rise time  CL = 1000pF 10% to 90% 9, 10, 11 3.5 7.5 ns
tLRC LO rise time  10% to 90% 9, 10, 11 3 7.5
tHFC HO fall time 90% to 10% 9, 10, 11 4 5.5
tLFC LO fall time  90% to 10% 9, 10, 11 3 5.5
tPW_IIM Minimum input pulse width (turn-on) MODE = IIM 9, 10, 11 5 8 ns
tPW_IIM_OFF Minimum input pulse width (turn-off) MODE = IIM 9, 10, 11 8 12 ns
tPW_PWM Minimum required input pulse width for targeted dead time (2) MODE = PWM, DT reduction ≤ 2ns RHL = 13.3kΩ 22 ns
tPW_PWM Minimum required input pulse width for targeted dead time (2) MODE = PWM, DT reduction ≤ 3ns RHL = 23.7kΩ 30 ns
(1) Subgroups are applicable for QML parts.  For subgroup definitions, see the Quality Conformance Inspection table.
(2) Specified by design; not tested in production.
(3) Specification limits for this parameter are represented as an absolute value.