JAJSEO3D June   2012  – February 2018 TPS81256

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     標準アプリケーション
    2.     効率と負荷電流との関係
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operation
      2. 8.3.2 Power-Save Mode
      3. 8.3.3 Current Limit Operation, Maximum Output Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Softstart, Enable
      2. 8.4.2 Load Disconnect and Reverse Current Protection
      3. 8.4.3 Undervoltage Lockout
      4. 8.4.4 Thermal Regulation
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Capacitor Selection CEXT
        2. 9.2.2.2 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Surface Mount Information
    4. 11.4 Thermal and Reliability Information
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIP|9
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Current Limit Operation, Maximum Output Current

The TPS81256 directly and accurately controls the average input current through intelligent adjustment of the valley current limit. The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off-time by sensing of the voltage drop across the synchronous rectifier.

The output voltage is reduced as the power stage of the device operates in a constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by Equation 1.

Equation 1. TPS81256 eq1_IoutDC_lvsaz9.gif

The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When the current limit is reached the output voltage decreases during further load increase.