JAJSEO3D June   2012  – February 2018 TPS81256

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
    1.     標準アプリケーション
    2.     効率と負荷電流との関係
  3. 概要
  4. 改訂履歴
  5. Device Options
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operation
      2. 8.3.2 Power-Save Mode
      3. 8.3.3 Current Limit Operation, Maximum Output Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Softstart, Enable
      2. 8.4.2 Load Disconnect and Reverse Current Protection
      3. 8.4.3 Undervoltage Lockout
      4. 8.4.4 Thermal Regulation
      5. 8.4.5 Thermal Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Capacitor Selection CEXT
        2. 9.2.2.2 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Surface Mount Information
    4. 11.4 Thermal and Reliability Information
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • SIP|9
サーマルパッド・メカニカル・データ
発注情報

Thermal and Reliability Information

The TPS81256 output current may need to be de-rated if it is required to operate in a high ambient temperature or deliver a large amount of continuous power. The amount of current de-rating is dependent upon the input voltage, output power and environmental thermal conditions. Care should especially be taken in applications where the localized PWB temperature exceeds 65°C.

The TPS81256 die and inductor temperature should be kept lower than the maximum rating of 125°C, so care should be taken in the circuit layout to ensure good heat sinking. Sufficient cooling should be provided to ensure reliable operation.

To estimate the junction temperature, approximate the power dissipation within the TPS81256 by applying the typical efficiency stated in this datasheet to the desired output power; or, by taking a power measurement if you have an actual TPS81256 device or a TPS81256EVM evaluation module. Then calculate the internal temperature rise of the TPS81256 above the surface of the printed circuit board by multiplying the TPS81256 power dissipation by the thermal resistance.

The thermal resistance numbers listed in the Thermal Information table are based on modeling the MicroSiP package mounted on a high-K test board specified per JEDEC standard. For increased accuracy and fidelity to the actual application, it is recommended to run a thermal image analysis of the actual system. Figure 24 and Figure 25 are thermal images of TI’s evaluation board with readings of the temperatures at specific locations on the device.

TPS81256 thermal2_lvsaz9.gifFigure 24. VIN=3.6v, VOUT=5v, IOUT=300ma
150mw Power Dissipation At Room Temperature
TPS81256 thermal3_lvsaz9.gifFigure 25. VIN=3.6v, VOUT=5v, IOUT=600ma
600mw Power Dissipation At Room Temperature

The TPS81256 is equipped with a thermal shutdown that will inhibit power switching at high junction temperatures. The activation threshold of this function, however, is above 125°C to avoid interfering with normal operation. Thus, it follows that prolonged or repetitive operation under a condition in which the thermal shutdown activates necessarily means that the components internal to the MicroSiP™ package are subjected to high temperatures for prolonged or repetitive intervals, which may damage or impair the reliability of the device.

MLCC capacitor reliability/lifetime is dependant on temperature and applied voltage conditions. At higher temperatures, MLCC capacitors are subject to stronger stress. On the basis of frequently evaluated failure rates determined at standardized test conditions, the reliability of all MLCC capacitors can be calculated for their actual operating temperature and voltage.

TPS81256 Capacitor_Guaranted_Lifetime_SLVSAZ9.pngFigure 26. Capacitor Lifetime vs Capacitor Case Temperature

Failures caused by systematic degradation can be described by the Arrhenius model. The most critical parameter (IR) is the Insulation Resistance (i.e. leakage current). The drop of IR below a lower limit (e.g. 1 MΩ) is used as the failure criterion, see Figure 26. It should be noted that the wear-out mechanisms occurring in the MLCC capacitors are not reversible but cumulative over time.