SLVSCE3A June   2014  – June 2014 TPS82740A , TPS82740B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Application
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. Table 1. Output Voltage Setting TPS82740A
    3. Table 2. Output Voltage Setting TPS82740B
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 DCS-Control
      2. 9.3.2 LOAD Switch
      3. 9.3.3 Output Voltage Selection (VSEL1, VSEL2, VSEL3)
      4. 9.3.4 Output Discharge Function (VOUT and LOAD)
      5. 9.3.5 Internal Current Limit
      6. 9.3.6 CTRL / DVS (Dynamic Voltage Scaling TPS62741)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable / Shutdown
      2. 9.4.2 Soft Start
      3. 9.4.3 POWER GOOD OUTPUT (PG)
      4. 9.4.4 Automatic Transition into 100% Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input Capacitor Selection
          1. 10.2.2.1.1 Input Buffer Capacitor Selection
        2. 10.2.2.2 Output Capacitor Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Surface Mount Information
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIP|9
サーマルパッド・メカニカル・データ
発注情報

9.4.3 POWER GOOD OUTPUT (PG)

The Power Good comparator features an open drain output. The PG comparator is active with EN pin set to high and VIN is above the threshold VTH_UVLO+. It is driven to high impedance once VOUT trips the threshold VTH_PG+ for rising VOUT. The output is pulled to low level once VOUT falls below the PG hysteresis, VPG_hys. The output is also pulled to low level in case the input voltage VIN falls below the undervoltage lockout threshold VTH_UVLO- or the device is disabled with EN = low. The power good output (PG) can be used as an indicator for the system to signal that the converter has started up and the output voltage is in regulation.

Table 4. PG condition table

Pin condition Operating condition Remark
PG EN CTRL IOUT / ILOAD VIN VOUT
hiz high high don't care > VUVLO VOUT > VTH_PG+ PG comparator active, pull up resistor pulls PG to high
hiz high low medium load (> 1mA) > VUVLO VOUT > VTH_PG+ PG comparator active, pull up resistor pulls PG to high
hiz high low light load (< 1mA) > VUVLO VOUT > VTH_PG+ PG comparator disabled for low Iq operation, pull up resistor pulls PG to high
low high don't care 0mA < IOUT < 100mA > VUVLO VOUT < VTH_PG- startup, overload or ramp down
low low don't care output disabled VIN > 1.2V VOUT = 0 device disabled
low high don't care output disabled < VUVLO VOUT not present device disabled, due to UVLO

Table 5. VOUT Output Discharge Condition Table

VOUT pin EN VIN condition remark
connected to GND, output discharged low 1.5V < VIN < VUVLO
connected to GND, output discharged high < VUVLO
hiz, discharge switch disabled high > VUVLO during regulator start up, the discharge switch is enabled and VOUT pulled to low, until the regulator start up time tStart expires. During the softstart time and later, the discharge switch is disabled.