JAJSF89C March   2013  – December 2019 TPS84A20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Ordering Information
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Package Specifications
    4. 7.4 Electrical Characteristics
    5. 7.5 Thermal Information
  8. 8 Device Information
    1. 8.1      Functional Block Diagram
    2. Table 1. Pin Descriptions
  9. 9 Typical Characteristics (PVIN = VIN = 12 V)
  10. 10Typical Characteristics (PVIN = VIN = 5 V)
  11. 11Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  12. 12Application Information
    1. 12.1  Adjusting the Output Voltage
    2. 12.2  Capacitor Recommendations for the TPS84A20 Power Supply
      1. 12.2.1 Capacitor Technologies
        1. 12.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 12.2.1.2 Ceramic Capacitors
        3. 12.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 12.2.2 Input Capacitor
      3. 12.2.3 Output Capacitor
    3. 12.3  Transient Response
    4. 12.4  Transient Waveforms
    5. 12.5  Application Schematics
    6. 12.6  VIN and PVIN Input Voltage
    7. 12.7  3.3 V PVIN Operation
    8. 12.8  Power Good (PWRGD)
    9. 12.9  Light Load Efficiency (LLE)
    10. 12.10 SYNC_OUT
    11. 12.11 Parallel Operation
    12. 12.12 Power-Up Characteristics
    13. 12.13 Pre-Biased Start-Up
    14. 12.14 Remote Sense
    15. 12.15 Thermal Shutdown
    16. 12.16 Output On/Off Inhibit (INH)
    17. 12.17 Slow Start (SS/TR)
    18. 12.18 Overcurrent Protection
    19. 12.19 Synchronization (CLK)
    20. 12.20 Sequencing (SS/TR)
    21. 12.21 Programmable Undervoltage Lockout (UVLO)
    22. 12.22 Layout Considerations
    23. 12.23 EMI
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 サポート・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報
    1. 14.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RVQ|42
サーマルパッド・メカニカル・データ
発注情報

12.20 Sequencing (SS/TR)

Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and PWRGD pins. The sequential method is illustrated in Figure 38 using two TPS84A20 devices. The PWRGD pin of the first device is coupled to the INH pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 39 shows sequential turnon waveforms of two TPS84A20 devices.

TPS84A20 slvsAW7_SequentialSeq.gifFigure 38. Sequencing Schematic
TPS84A20 waveformo_lvsa43.pngFigure 39. Sequencing Waveforms

Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 40 to the output of the power supply that needs to be tracked or to another voltage reference source. The tracking voltage must exceed 750 mV before VOUT2 reaches its set-point voltage.Figure 41 shows simultaneous turnon waveforms of two TPS84A20 devices. Use and to calculate the values of R1 and R2.

TPS84A20 slvsAW7_SimultSeq.gifFigure 40. Simultaneous Tracking Schematic
TPS84A20 waveformp_lvsa43.pngFigure 41. Simultaneous Tracking Waveforms