JAJSF89C March   2013  – December 2019 TPS84A20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Ordering Information
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Package Specifications
    4. 7.4 Electrical Characteristics
    5. 7.5 Thermal Information
  8. 8 Device Information
    1. 8.1      Functional Block Diagram
    2. Table 1. Pin Descriptions
  9. 9 Typical Characteristics (PVIN = VIN = 12 V)
  10. 10Typical Characteristics (PVIN = VIN = 5 V)
  11. 11Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  12. 12Application Information
    1. 12.1  Adjusting the Output Voltage
    2. 12.2  Capacitor Recommendations for the TPS84A20 Power Supply
      1. 12.2.1 Capacitor Technologies
        1. 12.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 12.2.1.2 Ceramic Capacitors
        3. 12.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 12.2.2 Input Capacitor
      3. 12.2.3 Output Capacitor
    3. 12.3  Transient Response
    4. 12.4  Transient Waveforms
    5. 12.5  Application Schematics
    6. 12.6  VIN and PVIN Input Voltage
    7. 12.7  3.3 V PVIN Operation
    8. 12.8  Power Good (PWRGD)
    9. 12.9  Light Load Efficiency (LLE)
    10. 12.10 SYNC_OUT
    11. 12.11 Parallel Operation
    12. 12.12 Power-Up Characteristics
    13. 12.13 Pre-Biased Start-Up
    14. 12.14 Remote Sense
    15. 12.15 Thermal Shutdown
    16. 12.16 Output On/Off Inhibit (INH)
    17. 12.17 Slow Start (SS/TR)
    18. 12.18 Overcurrent Protection
    19. 12.19 Synchronization (CLK)
    20. 12.20 Sequencing (SS/TR)
    21. 12.21 Programmable Undervoltage Lockout (UVLO)
    22. 12.22 Layout Considerations
    23. 12.23 EMI
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 サポート・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報
    1. 14.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RVQ|42
サーマルパッド・メカニカル・データ
発注情報

12.21 Programmable Undervoltage Lockout (UVLO)

The TPS84A20 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a typical hysteresis of 150 mV.

If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, then the UVLO pin can be configured as shown in Figure 42 or Figure 43. Table 9 lists standard values for RUVLO1 and RUVLO2 to adjust the VIN UVLO voltage up.

TPS84A20 slvsAW7_VinUVLO.gifFigure 42. Adjustable VIN UVLO
TPS84A20 slvsAW7_VinPVinUVLO.gifFigure 43. Adjustable VIN and PVIN Undervoltage Lockout

Table 9. Standard Resistor values for Adjusting VIN UVLO

VIN UVLO (V) 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1
RUVLO2 (kΩ) 21.5 18.7 16.9 15.4 14.0 13.0 12.1 11.3 10.5 9.76 9.31
Hysteresis (mV) 400 415 430 450 465 480 500 515 530 550 565

For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5 V. Figure 44 shows the PVIN UVLO configuration. Use Table 10 to select RUVLO1 and RUVLO2 for PVIN. If PVIN UVLO is set for less than 3.0 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V.

TPS84A20 slvsAW7_PVinUVLO.gifFigure 44. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V)

Table 10. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V)

PVIN UVLO (V) 2.9 3.0 3.5 4.0 4.5
RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1 For higher PVIN UVLO voltages, see Table 9 for resistor values.
RUVLO2 (kΩ) 47.5 44.2 34.8 28.7 24.3
Hysteresis (mV) 330 335 350 365 385