JAJSMG4A June   2023  – September 2023 TPS922052 , TPS922053 , TPS922054 , TPS922055

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adaptive Off-Time Current Mode Control
        1. 8.3.1.1 Switching Frequency Settings
        2. 8.3.1.2 Spread Spectrum
      2. 8.3.2 Setting LED Current
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Internal Soft Start
      5. 8.3.5 Dimming Mode
        1. 8.3.5.1 PWM Dimming
        2. 8.3.5.2 Analog Dimming
        3. 8.3.5.3 Hybrid Dimming
        4. 8.3.5.4 Flexible Dimming
      6. 8.3.6 CC/CV Charging Mode
      7. 8.3.7 Fault Protection
      8. 8.3.8 Thermal Foldback
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TPS922054 24-V Input, 4-A Output, 4-piece WLED Driver With Analog Dimming
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection
          2. 9.2.1.2.2 Input Capacitor Selection
          3. 9.2.1.2.3 Output Capacitor Selection
          4. 9.2.1.2.4 Sense Resistor Selection
          5. 9.2.1.2.5 Other External Components Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPS922054 48-V Input, 2-A Output, 12-piece WLED Driver with PWM Dimming
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Input Capacitor Selection
          3. 9.2.2.2.3 Output Capacitor Selection
          4. 9.2.2.2.4 Sense Resistor Selection
          5. 9.2.2.2.5 Other External Components Selection
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Layout Guidelines

An example of a proper layout for the TPS92205x family is shown in .セクション 9.4.2

  • Creating a large PGND plane for good electrical and thermal performance is important.
  • The IN and PGND traces should be as wide as possible to reduce trace impedance. Wide traces have the additional advantage of providing excellent heat dissipation.
  • Thermal vias can be used to connect the top-side PGND plane to additional printed-circuit board (PCB) layers for heat dissipation and grounding.
  • The input capacitors must be located as close as possible to the IN pin and the PGND/AGND pin.
  • The VCC capacitor should be placed as close as possible to VCC pin to ensure stable LDO output voltage.
  • The SW trace must be kept as short as possible to reduce parasitic inductance and thereby reduce transient voltage spikes. Short SW trace also reduces radiated noise and EMI.
  • Do not allow switching current to flow under the device.
  • The routing of CSN and CSP traces are recommended to be in parallel and kept as short as possible and placed away from the high-voltage switching trace and the ground shield.
  • The compensation capacitor must be placed as close as possible to COMP pin so as to prevent oscillation and system instability.