JAJSMG6A April 2023 – September 2023 TPS923652 , TPS923653 , TPS923654 , TPS923655
PRODUCTION DATA
The TPS92365x family supports analog dimming which regulates the LED current through the PWM input signal at the ADIM/HD pin. The analog dimming mode is enabled when the EN/PWM pin is always high and the ADIM/HD pin is configured by a PWM input signal.
The internal voltage reference, VREF, starts to rise after the first PWM pulse appears at the ADIM/HD pin. A 1-µs minimum on-time of the first PWM pulse is required for the internal digital circuits to enter the analog dimming mode. VREF continues to increase until the end of second PWM cycle and then changes to the desired value in proportion to the duty cycle of the PWM pulse. The minimum on-time of the PWM pulse after the first is 100 ns for the digital circuits to detect the duty cycle.
VREF is 200 mV when the PWM input signal at the ADIM/HD pin has a 100% duty cycle, for instance, and VREF is 20 mV when the PWM input signal has a 10% duty cycle. The initial change takes approximately 5 ms if VREF is 200 mV. The analog dimming enables 8-bit resolution which corresponds to 0.4% duty cycle step change at the ADIM/HD pin. Also, the circuit is able to respond to the duty cycle change of the PWM input signal with tens of micro-seconds delay.