SLUSCZ1 Data sheet

SLUSCZ1 May 2017 TPS92518-Q1

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PWP|24
- MPDS372A

サーマルパッド・メカニカル・データ

PWP|24
- PPTD111R

発注情報

8.4 Serial Interface

The 4-wire control interface is compatible with the Serial Peripheral Interface (SPI) bus. The control bus consists of four signals: SSN, SCK, MOSI, and MISO. The SSN, SCK, and MOSI pins are TTL inputs into the TPS92518-Q1 while the MISO pin is an open-drain output. The SPI bus can be configured for both star-connect and daisy chain hardware connections.

A bus transaction is initiated by a MCU on a falling edge of SSN. While SSN is low, the input data present on the MOSI pin is sampled on the rising edge of SCK, MSbit first. The output data is asserted on the MISO pin at the falling edge of SCK. The figure below shows the data transition and sampling edges of SCK.

A valid transfer requires a non-zero integer multiple of 16 SCK cycles (i.e., 16, 32, 48, etc.). If SSN is pulsed low and no SCK pulses are issued before SSN rises, a SPI error is reported. Similarly, if SSN is raised before the 16th rising edge of SCK, the transfer is aborted and a SPI error is reported. If SSN is held low after the 16th falling edge of SCK and additional SCK edges occur, the data continues to flow through the TPS92518-Q1 shift register and out the MISO pin. When SSN transitions from low-to-high, the internal digital block decodes the most recent 16 bits that were received prior to the SSN rising edge.

SSN must transition high only after a multiple of 16 SCK cycles for a transaction to be valid and not set the SPI error bit. In the case of a write transaction, the TPS92518-Q1 logic performs the requested operation when SSN transitions high. In the case of a read transaction, the read data is transferred during the next frame, regardless of whether a SPI error has occurred.

Figure 33. SPI Data Format

The data bit on MOSI is shifted into an internal 16-bit shift register (MSbit first) while data is simultaneously shifted out the MISO pin. While SSN is high (bus idle), MISO is tri-stated by the open-drain driver. While SSN is low, MISO is driven according to the 16-bit data pattern being shifted out based on the prior received command. At the falling edge of SSN to begin a new transaction, MISO is driven to the MSbit of the outbound data, and is updated on each subsequent falling edge of SCK.

NOTE

The first MISO transition happens on the first falling edge AFTER the first rising edge of SCK.