JAJSR45 august   2023 TPS92621-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply (SUPPLY)
        1. 7.3.1.1 Power-On Reset (POR)
        2. 7.3.1.2 Suppply Current in Fault Mode
      2. 7.3.2  Enable and Shutdown(EN)
      3. 7.3.3  Constant-Current Output and Setting (IN)
      4. 7.3.4  Thermal Sharing Resistor (OUT and RES)
      5. 7.3.5  PWM Control (PWM)
      6. 7.3.6  Supply Control
      7. 7.3.7  Diagnostics
        1. 7.3.7.1 LED Short-to-GND Detection
        2. 7.3.7.2 LED Open-Circuit Detection
        3. 7.3.7.3 LED Open-Circuit Detection Enable (DIAGEN)
        4. 7.3.7.4 Overtemperature Protection
        5. 7.3.7.5 Low Dropout Operation
      8. 7.3.8  FAULT Bus Output With One-Fails-All-Fail
      9. 7.3.9  FAULT Table
      10. 7.3.10 LED Fault Summary
      11. 7.3.11 IO Pins Inner Connection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout, V(SUPPLY) < V(POR_rising)
      2. 7.4.2 Normal Operation V(SUPPLY) ≥ 4.5 V
      3. 7.4.3 Low-Voltage Dropout Operation
      4. 7.4.4 Fault Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 BCM Controlled Rear Lamp With One-Fails-All-Fail Setup
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Independent PWM Controlled Rear Lamp By MCU
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

V(SUPPLY) = 5 V to 40 V, TJ = –40°C to +150°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(POR_rising) Supply voltage POR rising threshold 3.6 4.0 V
V(POR_falling) Supply voltage POR falling threshold 3.0 3.4 V
I(SD) Device shutdown current V(EN)= 0V 11.4 15.0 uA
I(Quiescent) Device standby ground current PWM = HIGH 0.7 1.0 mA
I(FAULT) Device supply current in fault mode PWM = HIGH, FAULT externally pulled LOW 0.21 0.27 0.35 mA
LOGIC INPUTS (DIAGEN, PWM, EN)
VIL(EN) Input logic-low voltage, EN 0.7 V
VIH(EN) Input logic-high voltage, EN 2.0 V
I(EN_pulldown) EN pulldown current V(EN) = 12 V 1.5 2.9 4.5 uA
VIL(DIAGEN) Input logic-low voltage, DIAGEN 1.045 1.1 1.155 V
VIH(DIAGEN) Input logic-high voltage, DIAGEN 1.14 1.2 1.26 V
VIL(PWM) Input logic-low voltage, PWM 1.045 1.1 1.155 V
VIH(PWM) Input logic-high voltage, PWM 1.14 1.2 1.26 V
CONSTANT-CURRENT DRIVER
I(OUTx_Tot) Device output-current for each channel 100% duty cycle 5 300 mA
V(CS_REG) Sense-resistor regulation voltage TA = –40°C to +125°C 144 150 156 mV
ALL ΔV(CS_d2d) Device to device mismatch ΔV(CS_d2d) = 1 – V(CS_REG) / Vnom(CS_REG) –4 +4 %
R(CS_REG) Sense-resistor range 0.48 31.2 Ω
V(DROPOUT) Voltage dropout from IN to OUT, RES open current setting of 150 mA 50 170 300 mV
current setting of 300 mA 100 342 600 mV
Voltage dropout from IN to RES, OUT open current setting of 150 mA 100 350 600 mV
current setting of 300 mA 100 710 1200 mV
I(RES) Ratio of RESx current to total current I(RES)/I(OUT_Tot), V(IN) – V(RES) > 1 V, Itotal=150mA 95 %
DIAGNOSTICS
V(OPEN_th_rising) LED open rising threshold, V(IN) – V(OUT) 180 320 420 mV
V(OPEN_th_falling) LED open falling threshold, V(IN) – V(OUT) 510 mV
V(SG_th_rising) Channel output short-to-ground rising threshold 1.14 1.2 1.26 V
V(SG_th_falling) Channel output short-to-ground falling threshold 0.855 0.9 0.945 V
I(Retry_OUT) Channel output V(OUT) short-to-ground retry current 0.64 1.10 1.528 mA
I(Retry_RES) Channel output V(RES) short-to-ground retry current 0.64 1.10 1.528 mA
FAULT
VIL(FAULT) Logic input low threshold 0.7 V
VIH(FAULT) Logic input high threshold 2 V
t(FAULT_rising) Fault detection rising edge deglitch time 10 µs
t(FAULT_falling) Fault detection falling edge deglitch time 20 µs
I(FAULT_pulldown) FAULT internal pulldown current V(FAULT) = 0.4 V 2 3 4 mA
I(FAULT_pullup) FAULT internal pullup current 6 10 14 µA
I(FAULT_leakage) FAULT leakage current V(FAULT) = 40 V 1 µA
TIMING
t(PWM_delay_rising) PWM rising edge delay to 10% of output current, t1 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 0.6 Ω, and R(RES) = 39 Ω 3.7 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 30 Ω and R(RES) = 56 Ω 2.2 µs
t(PWM_delay_falling) PWM falling edge delay to 90% of output current, t2 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 0.6 Ω, and R(RES) = 39 Ω 4.0 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 30 Ω and R(RES) = 56 Ω 3.6 µs
t(Current_rising) Output current rising from 10% to 90%, t3 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 0.6 Ω, and R(RES) =39 Ω 1.8 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 30 Ω and R(RES) = 56 Ω 1.8 µs
t(Current_falling) Output current falling from 90% to 10%, t4 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 0.6 Ω, and R(RES) = 39 Ω 5.7 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 30 Ω and R(RES) = 56 Ω 0.3 µs
t(STARTUP) SUPPLY rising edge to 10% output current, t5 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 0.6 Ω, and R(RES) = 39 Ω 96 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNS) = 30 Ω and R(RES) = 56 Ω 85 µs
t(OPEN_deg) LED-open fault detection deglitch time, t6 as shown in Figure 7-4 125 µs
t(SG_deg) Output short-to-ground detection deglitch time, t7 as shown in Figure 7-3 125 µs
t(Recover_deg) Open and Short fault recovery deglitch time, t8 as shown in Figure 7-4 and  Figure 7-3 125 µs
t(FAULT_deg) Fault pin deglitch time 20 µs
t(FAULT_recovery) Fault recovery delay time, t9 as shown in Figure 7-4 and Figure 7-3 50 µs
t(TSD_deg) Thermal over temperature deglitch time 50 µs
THERMAL PROTECTION
T(TSD) Thermal shutdown junction temperature threshold 157 172 187 °C
T(TSD_HYS) Thermal shutdown junction temperature hysteresis 15 °C