JAJSC31E February   2014  – May 2018 TPS92630-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Constant LED-Current Setting
      2. 9.3.2 PWM Control
      3. 9.3.3 FAULT Diagnostics
      4. 9.3.4 Short-Circuit Detection
      5. 9.3.5 Open-Load Detection
      6. 9.3.6 Thermal Foldback
    4. 9.4 Device Functional Modes
      1. 9.4.1 Thermal Information
      2. 9.4.2 Operation With V(VIN) < 5 V (Minimum V(VIN))
      3. 9.4.3 Operation With 5 V < V(VIN) < 9 V (Lower-Than-Normal Automotive Battery Voltage)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stoplight and Taillight Application With PWM Generator
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step-by-Step Design Procedure
            1. 10.2.1.2.1.1 R(REF)
            2. 10.2.1.2.1.2 Duty Cycle
            3. 10.2.1.2.1.3 Input and Output Capacitors
        3. 10.2.1.3 PWM Dimming Application Curve
      2. 10.2.2 Simple Stop-Light and Taillight Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Step-by-Step Design Procedure
            1. 10.2.2.2.1.1 R(REF)
            2. 10.2.2.2.1.2 R(Stop)
            3. 10.2.2.2.1.3 Input and Output Capacitors
      3. 10.2.3 Parallel Connection
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Step-by-Step Design Procedure
            1. 10.2.3.2.1.1 R(REF)
            2. 10.2.3.2.1.2 Input and Output Capacitors
      4. 10.2.4 Alternate Parallel Connection
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Step-by-Step Design Procedure
            1. 10.2.4.2.1.1 R(REF)
            2. 10.2.4.2.1.2 Input and Output Capacitors
      5. 10.2.5 High-Side PWM Dimming
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Step-by-Step Design Procedure
            1. 10.2.5.2.1.1 Ratio of Resistors, R1 / R2
            2. 10.2.5.2.1.2 R1 and R2 Selection
            3. 10.2.5.2.1.3 Input and Output Capacitors
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.3 FAULT Diagnostics

The TPS92630-Q1 device has two fault pins, FAULT and FAULT_S. FAULT_S is a dedicated fault pin for single-LED short failure and FAULT is for general faults, that is, short, open, and thermal shutdown. The dual pins allow maximum flexibility based on all requirements and application conditions.

The device fault pins can be connected to an MCU for fault reporting. Both fault pins are open-drain transistors with a weak internal pullup. See Figure 19.

TPS92630-Q1 det_tim_dia_1_SLVSC76.gifFigure 18. Detailed Timing Diagram

In case there is no MCU, one can connect up to 15 TPS92630-Q1 FAULT and FAULT_S pins together. When one or more devices have errors, the respective FAULT̅ pins go low, pulling the connected FAULT bus down and shutting down all device outputs. Figure 19 shows the fault-line bus connection.

TPS92630-Q1 fau_lin_conn_SLVSC76.gifFigure 19. Fault-Line Bus Connection

The device releases the FAULT bus when external circuitry pulls the FAULT pin high, on toggling of the EN pin, or on a power cycle of the device. In case there is no MCU, only a power cycle clears the fault. See Figure 20.

TPS92630-Q1 det_tim_dia_2_SLVSC76.gifFigure 20. Detailed Timing Diagram

The following faults result in the FAULT or FAULT_S pin going low: thermal shutdown, open load, output short circuit, single LED short, and REF open or shorted. For thermal shutdown or LED open, release of the FAULT pin occurs when the thermal-shutdown or LED-open condition no longer exists. For other faults, the FAULT and FAULT_S pins stay low even if the condition does not exist. Clearing the faults requires a power cycle of the device.