JAJSHS0C March   2019  – March 2021 TPS92682-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable
      2. 7.3.2  Internal Regulator and Undervoltage Lockout (UVLO)
      3. 7.3.3  Oscillator
      4. 7.3.4  Spread Spectrum Function
      5. 7.3.5  Gate Driver
      6. 7.3.6  Rail-to-Rail Current Sense Amplifier
      7. 7.3.7  Transconductance Error Amplifier
      8. 7.3.8  Switch Current Sense
      9. 7.3.9  Slope Compensation
      10. 7.3.10 ILED Setting in CC Mode
      11. 7.3.11 Output Voltage Setting in CV Mode
      12. 7.3.12 PWM Dimming
      13. 7.3.13 P-Channel FET Gate Driver Output
      14. 7.3.14 Soft Start
      15. 7.3.15 Two-Phase Operation
        1. 7.3.15.1 Current Sharing In Two-Phase
      16. 7.3.16 Faults and Diagnostics
        1. 7.3.16.1  Main Fault Timer (MFT)
        2. 7.3.16.2  OV Fault
        3. 7.3.16.3  UV Fault
        4. 7.3.16.4  ILIM Fault
        5. 7.3.16.5  UVLO
        6. 7.3.16.6  ILED Over Current (OC)
        7. 7.3.16.7  ILED Undercurrent (UC)
        8. 7.3.16.8  ISNOPEN, FBOPEN, and RTOPEN Faults
        9. 7.3.16.9  TW and TSD
        10. 7.3.16.10 COMPx Pull-Down and Comp-Low signal
    4. 7.4 Device Functional Modes
      1. 7.4.1 POR Mode
      2. 7.4.2 Normal Operation
      3. 7.4.3 Limp Home
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Command Frame
      3. 7.5.3 Response Frame
        1. 7.5.3.1 Read Response Frame Format
        2. 7.5.3.2 Write Response Frame Format
        3. 7.5.3.3 Write Error/POR Frame Format
      4. 7.5.4 SPI Error
    6. 7.6 TPS92682 Registers
      1. 7.6.1  EN Register
      2. 7.6.2  CFG1 Register
      3. 7.6.3  CFG2 Register
      4. 7.6.4  SWDIV Register
      5. 7.6.5  ISLOPE Register
      6. 7.6.6  FM Register
      7. 7.6.7  SOFTSTART Register
      8. 7.6.8  CH1IADJ Register
      9. 7.6.9  CH2IADJ Register
      10. 7.6.10 PWMDIV Register
      11. 7.6.11 CH1PWML Register
      12. 7.6.12 CH1PWMH Register
      13. 7.6.13 CH2PWML Register
      14. 7.6.14 CH2PWMH Register
      15. 7.6.15 ILIM Register
      16. 7.6.16 IFT Register
      17. 7.6.17 MFT Register
      18. 7.6.18 FLT1 Register (read only)
      19. 7.6.19 FLT2 Register (read only)
      20. 7.6.20 FEN1 Register
      21. 7.6.21 FEN2 Register
      22. 7.6.22 FLATEN Register
      23. 7.6.23 OV Register
      24. 7.6.24 LHCFG Register
      25. 7.6.25 LHCH1IADJ Register
      26. 7.6.26 LHCH2IADJ Register
      27. 7.6.27 LHCH1PWML Register
      28. 7.6.28 LHCH1PWMH Register
      29. 7.6.29 LHCH2PWML Register
      30. 7.6.30 LHCH2PWMH Register
      31. 7.6.31 LHILIM Register
      32. 7.6.32 LHIFT Register
      33. 7.6.33 LHMFT Register
      34. 7.6.34 LHFEN1 Register
      35. 7.6.35 LHFEN2 Register
      36. 7.6.36 LHFLATEN Register
      37. 7.6.37 LHOV Register
      38. 7.6.38 CAL Register
      39. 7.6.39 RESET Register
  8. 8 Application and Implementation
    1. 8.1 Application Information General Design Considerations
      1. 8.1.1 Switching Frequency, fSW
      2. 8.1.2 Duty Cycle Considerations
      3. 8.1.3 Main Power MOSFET Selection
      4. 8.1.4 Rectifier Diode Selection
      5. 8.1.5 Switch Current Sense Resistor
      6. 8.1.6 Slope Compensation
      7. 8.1.7 Soft Start
    2. 8.2 Application Information CC Mode
      1. 8.2.1 Inductor Selection
      2. 8.2.2 Output Capacitor Selection
      3. 8.2.3 Input Capacitor Selection
      4. 8.2.4 Programming LED Current
      5. 8.2.5 Feedback Compensation
      6. 8.2.6 Overvoltage and Undervoltage Protection
      7. 8.2.7 Series P-Channel MOSFET Selection
      8. 8.2.8 Programming Example for Two-Channel CC Mode
    3. 8.3 Typical Application CV Mode
      1. 8.3.1 Inductor Selection
      2. 8.3.2 Output Capacitor Selection
      3. 8.3.3 Input Capacitor Selection
      4. 8.3.4 Programming Output Voltage VOUT
      5. 8.3.5 Feedback Compensation
      6. 8.3.6 Overvoltage and Undervoltage Protection
      7. 8.3.7 Programing Example for Two-Phase CV BOOST
    4. 8.4 Typical Application CC Mode
      1. 8.4.1 CC Boost Design Requirements
      2. 8.4.2 CC Boost Detailed Design Procedure
        1. 8.4.2.1  Calculating Duty Cycle
        2. 8.4.2.2  Setting Switching Frequency
        3. 8.4.2.3  Setting Dither Modulation Frequency
        4. 8.4.2.4  Inductor Selection
        5. 8.4.2.5  Output Capacitor Selection
        6. 8.4.2.6  Input Capacitor Selection
        7. 8.4.2.7  Main N-Channel MOSFET Selection
        8. 8.4.2.8  Rectifier Diode Selection
        9. 8.4.2.9  Setting ILED and Selecting RCS
        10. 8.4.2.10 Setting Switch Current Limit
        11. 8.4.2.11 Slope Compensation
        12. 8.4.2.12 Compensator Parameters
        13. 8.4.2.13 Overvoltage Protection
        14. 8.4.2.14 Series P-Channel MOSFET Selection
      3. 8.4.3 CC Buck-Boost Design Requirements
      4. 8.4.4 CC Buck-Boost Detailed Design Procedure
        1. 8.4.4.1  Calculating Duty Cycle
        2. 8.4.4.2  Setting Switching Frequency
        3. 8.4.4.3  Setting Dither Modulation Frequency
        4. 8.4.4.4  Inductor Selection
        5. 8.4.4.5  Output Capacitor Selection
        6. 8.4.4.6  Input Capacitor Selection
        7. 8.4.4.7  Main N-Channel MOSFET Selection
        8. 8.4.4.8  Rectifier Diode Selection
        9. 8.4.4.9  Setting ILED and Selecting RCS
        10. 8.4.4.10 Setting Switch Current Limit
        11. 8.4.4.11 Slope Compensation
        12. 8.4.4.12 Compensator Parameters
        13. 8.4.4.13 Overvoltage Protection
      5. 8.4.5 PWM Dimming Consideration
      6. 8.4.6 Application Curves
    5. 8.5 Typical Application CV Mode
      1. 8.5.1 CV Design Requirements
      2. 8.5.2 Detailed Design Procedure
        1. 8.5.2.1  Calculating Duty Cycle
        2. 8.5.2.2  Setting Switching Frequency
        3. 8.5.2.3  Setting Dither Modulation Frequency
        4. 8.5.2.4  Inductor Selection
        5. 8.5.2.5  Output Capacitor Selection
        6. 8.5.2.6  Input Capacitor Selection
        7. 8.5.2.7  Main N-Channel MOSFET Selection
        8. 8.5.2.8  Rectifier Diode Selection
        9. 8.5.2.9  Programming VOUT
        10. 8.5.2.10 Setting Switch Current Limit
        11. 8.5.2.11 Slope Compensation
        12. 8.5.2.12 Compensator Parameters
        13. 8.5.2.13 Overvoltage Protection
      3. 8.5.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.8 Switch Current Sense

Figure 7-9 shows the simplified block diagram of the switch current sense circuitry. The ISPx input pin monitors the main MOSFET current to implement peak current mode control. The GATEx output duty cycle is derived by comparing the peak switch current, measured by the RIS resistor, to the internal CHx_COMP voltage threshold. An internal slope signal, CHx_ISLOPE, is added to the measured sense voltage to prevent sub-harmonic oscillations for duty cycles greater than 50%.

An internal leading-edge blanking (LEB) is applied to the switch current sense at the beginning of each switching cycle by shunting the ISPx input to the ISNx (GND connection of the RIS) for the duration of the LEB time. The LEB circuit prevents unwanted duty cycle termination due to MOSFET switching-current spike at the beginning of the new switching cycle. The LEB time can be set to 150 ns or 75 ns (typical) using the CHxLEB bit set in Table 7-5. For additional noise suppression, connect an external low-pass RC filter with resistor values ranging from 100 Ω to 500 Ω and a 1000-pF capacitor across RIS.

Cycle-by-cycle current limit is accomplished by a separate internal comparator. The current limit threshold is set based on the status of internal PWM signal and the CHxILIM setting. The current limit threshold is set to a value programmed in the CHxILIM in Table 7-17 when PWM signal is high. The current limit threshold is set to 700 mV (typical) when PWM signal is low. In CC mode, the transition between the two thresholds in conjunction with the slope compensation and the error amplifier circuit allows for higher inductor current immediately after the PWM transition, to improve LED current transient response in PWM dimming.

The device immediately terminates the GATEx and PDRVx outputs when the sensed voltage at the ISPx input exceeds the current limit threshold. For more detail on the cycle-by-cycle current limit, refer to the Faults and Diagnostics section.

GUID-B48D37A6-3DE2-46FE-A759-898089CA4EA9-low.gifFigure 7-9 Switch Current Sense and Current Limit