JAJSHS0C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
For each channel of the TPS92682-Q1, there is a 14-bit counter that implements a main fault timer. The timer can be programmed by a 4-bit value for each channel in the MFT Register. The MFT time can be set to a value between 1000 and 16383 times the input clock period. The input clock of the MFT is the channel clock, CHxCLK (the switching frequency fSW). For example, for a channel with a switching frequency of fSW = 400 kHz, the timer can be programmed from 2.5 to 41 ms.
Only UV and OC faults can trigger the MFT. When either of these two faults are enabled as a non-latched fault, the fault event turns off the channel and triggers the MFT. The associated channel is turned back on by a soft-start process when the MFT count is completed and the fault is cleared.