As shown in Figure 7-10, the TPS92682-Q1 device incorporates both internal and external PWM dimming. To select between external or internal PWM dimming, the INTPWM bit in CFG1 Register must be set to "0" or "1", respectively. If internal PWM dimming operation is selected, the state of the PWMx pins do not have any effect on the operation of the device. For external PWM dimming, apply a square-wave signal to the PWMx pin with the rising and falling thresholds provided in the Electrical Characteristics. The LED current modulates based on the duty cycle of the external PWM signal, D_PWM(EXT).

Figure 7-10 PWM Dimming Circuit

To use internal PWM dimming, the INTPWM bit in CFG1 Register must be set to "1". The TPS92682-Q1 device incorporates a 10-bit PWM counter for each channel. The duty cycle of the internal PWM can be set using a 10-bit value in the CHxPWML and CHxPWMH registers. Because CHxPWM is a 10-bit value, a PWM duty cycle update can require two SPI writes, one to the CHxPWMH and another to the CHxPWML register. To prevent transferring incoherent values, the contents of the two registers transfer to the CHxPWM counter only upon the write to the CHxPWML register. Therefore, for an update to the PWM duty cycle, it is recommended consecutively writing to CHxPWMH first and CHxPWML second. In addition, in order to avoid corrupting the progress of the current PWM duty cycle, the update from the CHxPWM registers to the CHxPWM counter occurs two PWM_CLK before the end of each PWM period (at the count of 1022).

Due to synchronization of the external PWM with internal clock, when switching from external PWM to internal PWM, a glitch for the total of one PWM period can be observed in the output.

The clock to the 10-bit PWM counter is related to the main clock, CLK_M, by a division factor set by a 3-bit value in the PWMDIV Register. The relation between the PWM_CLK and PWM frequency with CLK_M frequency are shown in Equation 3 and Equation 4.

Equation 3.

Equation 4.

For example, if the CLK_M frequency is set to f_CLKM = 800 kHz and PWM_DIV = 001 (division value of 2), the PWM frequency is PWM_FREQ ≈ 390 Hz.

The phase between the internal PWM dimming for the two channels can be set to 180° if the PWMPH bit in CFG1 Register is set to 0. For PWMPH = 1, there is zero phase shift between the internal 10-bit PWM counters of the two channels.

The PWM signal controls the GATEx and PDRVx outputs. If PWM_xINT is set low, the associated channel is turned off, the COMPx pin is disconnected from the error amplifier, and the PDRVx output is set to V_CSP to maintain the charge on the compensation network and output capacitors. On the rising edge of the PWM_xINT, the GATEx and PDRVx outputs are enabled to ramp the inductor current to the previous steady-state value. The COMPx pin connects to the error amplifier only when the switch current sense voltage V_ISPx exceeds the COMPx voltage, CHx_comp. This connection immediately forces the converter into steady-state operation with minimum LED current overshoot. When dimming is not required, connect the PWMx pins to the VDD pin. An internal pull-down resistor sets the PWM inputs to logic-low and disables the device when the pins are disconnected or left floating, and the INTPWM bit in CFG1 Register is set to the default value of "0".