TPS92692, TPS92692-Q1 High Accuracy LED Controller With Spread Spectrum Frequency Modulation

1 Features

Wide Input Voltage: 4.5 V to 65 V
Better than ± 4% LED Current Accuracy over –40°C to 150°C Junction Temperature Range
Spread Spectrum Frequency Modulation for Improved EMI
Comprehensive Fault Protection Circuitry with Current Monitor output and Open Drain Fault Flag Indicator
Internal Analog Voltage to PWM Duty Cycle Generator for stand-alone Dimming Operation
Compatible with Direct PWM Input with over 1000:1 Dimming Range
Analog LED Current Adjust Input (IADJ) with over 15:1 Contrast Ratio
Integrated P-Channel Driver to enable Series FET Dimming and LED Protection
TPS92692-Q1: Automotive Q100 Grade 1 Qualified

2 Applications

TPS92692-Q1: Automotive Exterior Lighting Applications
Driver Monitoring Systems (DMS)
LED General Lighting Applications
Exit Signs and Emergency Lighting

3 Description

The TPS92692 and TPS92692-Q1 are high accuracy peak current mode based controllers designed to support step-up/down LED driver topologies. The device incorporates a rail-to-rail current amplifier to measure LED current and spread spectrum frequency modulation technique for improved EMI performance.

This high performance LED controller can independently modulate LED current using either analog or PWM dimming techniques. Linear analog dimming response with over 15:1 range is obtained by varying the voltage across the high impedance analog adjust (IADJ) input. PWM dimming of LED current is achieved by directly modulating the DIM/PWM input pin with the desired duty cycle or by enabling the internal PWM generator circuit. The PWM generator translates the DC voltage at DIM/PWM pin to corresponding duty cycle by comparing it to the internal triangle wave generator. The optional PDRV gate driver output can be used to drive an external P-Channel series MOSFET.

The TPS92692 and TPS92692-Q1 devices support continuous LED status check through the current monitor (IMON) output. The devices also include an open drain fault indicator output to indicate LED overcurrent, output overvoltage and output undervoltage conditions.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS92692-Q1	HTSSOP (20)	5.10 mm × 6.60 mm
TPS92692	HTSSOP (20)	5.10 mm × 6.60 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Boost LED Driver

4 Revision History

DATE	REVISION	NOTES
March 2017	*	Initial release.

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP with PowerPAD™

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COMP	7	I/O	Transconductance error amplifier output. Connect compensation network to achieve desired closed-loop response.
CSN	13	I	Current sense amplifier negative input (–). Connect directly to the negative node of LED current sense resistor, R_CS.
CSP	14	I	Current sense amplifier positive input (+). Connect directly to the positive node of LED current sense resistor, R_CS.
DIM/PWM	10	I	External analog to PWM dimming command or direct PWM dimming input. The external analog dimming command between 1 V and 3 V is compared to the internal PWM generator triangle waveform to set LED current duty cycle between 0% and 100%. With PWM generator disabled, a direct PWM dimming command can be applied to control the LED current duty cycle and frequency. The analog or PWM command is used to generate an internal PWM signal that controls the GATE and PDRV outputs. Setting the internal PWM signal to logic level low, turns off switching, idles the oscillator, disconnects the COMP pin, and sets PDRV to V_CSP. Connect to VREF when not used for PWM dimming.
DM	5	I/O	Triangle wave spread spectrum modulation frequency, f_m, programming pin. Connect a capacitor to GND to set the spread spectrum modulating frequency. Connect directly to GND to disable spread spectrum modulation of switching frequency.
FLT	3	O	Open-drain fault indicator. Connect to VREF with a resistor to create active low fault signal output. Internal LED short circuit protection and auto-restart timer can enabled by directly connecting the pin to SS input.
GATE	19	O	N-channel MOSFET gate driver output. Connect to gate of external main switching N-channel MOSFET.
GND	17	—	Analog and Power ground connection pin. Connect to circuit ground to complete return path.
IADJ	9	I	LED current reference input. Connect this pin to VCC with a 100-kΩ series resistor to set the internal reference voltage to 2.42 V and the current sense threshold, V_(CSP-CSN) to 170.7 mV. The pin can be modulated by an external voltage source from 140 mV to 2.25 V to implement analog dimming.
IMON	8	O	LED current report pin. The LED current sensed by CSP/CSN input is reported as V_IMON = 14 × I_LED × R_CS. Bypass with a 1-nF ceramic capacitor connected to GND.
IS	18	I	Switch current sense input. Connect to the switch sense resistor, R_IS to set the switch current limit threshold based on the internal 250 mV reference.
OV	15	I	Output voltage input. Connect a resistor divider from output voltage to GND to set output overvoltage and under-voltage protection thresholds.
PDRV	12	O	Series dimming P-channel FET gate driver output. Connect to gate of external P-channel MOSFET to implement series FET PWM dimming and fault disconnect.
RAMP	11	I/O	Programming input for internal PWM generator. Connect a capacitor to GND to set the triangle wave frequency for PWM generator circuit. Connect a 249-kΩ resistor to GND to disable the PWM generator and to set a fixed reference for direct external PWM dimming input. Do not allow this pin to float.
RT	6	I/O	Oscillator frequency programming pin. Connect a resistor to GND to set the switching frequency. The internal oscillator can be synchronized by coupling an external clock pulse through a series capacitor with a value of 100 nF.
SLOPE	16	I/O	Slope compensation input. Connect a resistor to GND to set the desired slope compensation ramp based on inductor value, input and output voltages.
SS	4	I/O	Soft-start programming pin. Connect a capacitor to GND to extend the start-up time. Switching can be disabled by shorting this pin to GND.
VCC	20	—	VCC (7.5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a value between 2.2-µF and 4.7-µF). Locate close to the controller.
VIN	1	—	Input supply for the internal regulators. Bypass with a low-pass filter using a series 10-Ω resistor and 10- nF capacitor connected to GND. Locate the capacitor close to the controller.
VREF	2	—	VREF (5 V) bias supply pin. Locally decouple to GND using a ceramic capacitor (with a value between 2.2-µF and 4.7-µF) located close to the controller.
Thermal Pad		—	The GND pin must be connected to the exposed thermal pad for proper operation. This PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Input voltage	VIN, CSP, CSN	–0.3	65	V
	DIM/PWM	–0.3	14	V
	IS, RT, FLT	–0.3	8.8	V
	OV, SS, RAMP, DM, SLOPE, VREF, IADJ	–0.3	5.5	V
	CSP to CSN⁽³⁾	–0.3	0.3	V
Output voltage⁽⁴⁾	VCC, GATE	–0.3	8.8	V
	PDRV	V_CSP – 8.8	V_CSP	V
	COMP	–0.3	5.0	V
Source current	IMON	—	100	µA
	GATE (pulsed < 20 ns)	—	500	mA
	PDRV (pulsed < 10 µs)	—	50	mA
Sink current	GATE (pulsed < 20 ns)	—	500	mA
Sink current	PDRV (pulsed < 10 µs)	—	50	mA
Operating junction temperature, T_J		–40	150	°C
Storage temperature, T_stg			165	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted

(3) Continuous sustaining voltage

(4) All output pins are not specified to have an external voltage applied.

6.2 ESD Ratings

				VALUE	UNIT
TPS92692-Q1 IN PWP (HTSSOP) PACKAGE
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002, all pins⁽¹⁾		±2000	V
		Charged-device model (CDM), per AEC Q100-011	All pins except 1, 10, 11, and 20	±500
		Charged-device model (CDM), per AEC Q100-011	Pins 1, 10, 11, and 20	±750
TPS92692 IN PWP (HTSSOP) PACKAGE
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾		±500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
VIN	Supply input voltage	6.5	14	65	V
VIN, crank	Supply input, battery crank voltage	4.5			V
V_CSP, V_CSN	Current sense common mode	6.5		60	V
ƒ_SW	Switching frequency	80		800	kHz
ƒ_m	Spread spectrum modulation frequency	0.1		12	kHz
f_RAMP	Internal PWM ramp generator frequency	100		2000	Hz
V_IADJ	Current reference voltage	0.14		V_IADJ(CLAMP)	V
T_A	Operating ambient temperature	–40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS92692	TPS92692-Q1	UNIT
		PWP (HTSSOP)	PWP (HTSSOP)
		20 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	40.8	40.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	26.1	26.1	°C/W
R_θJB	Junction-to-board thermal resistance	22.2	22.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.8	0.8	°C/W
ψ_JB	Junction-to-board characterization parameter	22.0	22.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.3	2.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

–40°C ≤ T_J ≤ 150°C, V_IN = 14 V, V_IADJ = 2.1 V, V_RAMP = 500 mV, V_DIM/PWM = 3 V, V_OV = 500 mV, C_VCC = 1 µF, C_VREF = 1 µF, C_COMP = 2.2 nF, R_CS = 100 mΩ, R_T = 20 kΩ, no load on GATE and PDRV (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT VOLTAGE (VIN)
I_IN(STBY)	Input stand-by current	V_PWM = 0 V		1.8	2.5	mA
I_IN(SW)	Input switching current	V_CC = 7.5 V, C_GATE = 1 nF		5.1	6.6	mA
BIAS SUPPLY (VCC)
V_CC(REG)	Regulation voltage	No load	7.0	7.5	8.0	V
V_CC(UVLO)	Supply undervoltage protection	VCC rising threshold, V_IN = 8 V		4.5	4.9	V
		VCC falling threshold, V_IN = 8 V	3.7	4.1		V
		Hysteresis		400		mV
I_CC(LIMIT)	Supply current limit	V_CC = 0 V	30	36	46	mA
V_DO	LDO dropout voltage	I_CC = 20 mA, V_IN = 5 V		300		mV
REFERENCE VOLTAGE (VREF)
VREF	Reference voltage	No load	4.77	4.96	5.15	V
I_REF(LIMIT)	Current limit	V_REF = 0 V	30	36	46	mA
OSCILLATOR (RT)
ƒ_SW	Switching frequency	R_T = 40 kΩ	175	200	225	kHz
ƒ_SW	Switching frequency	R_T = 20 kΩ	341	390	439	kHz
V_RT	RT output voltage			1		V
V_SYNC	SYNC rising threshold	V_RT rising		2.5	3.1	V
V_SYNC	SYNC falling threshold	V_RT falling	1.8	2		V
t_SYNC(MIN)	Minimum SYNC clock pulse width			100		ns
SPREAD SPECTRUM FREQUENCY MODULATION (DM)
I_DM	Triangle wave generator sink current			10		µA
I_DM	Triangle wave generator source current			10		µA
V_DM(TR)	Triangle wave voltage peak (High)			1.15		V
V_DM(TR)	Triangle wave voltage valley (Low)			850		mV
V_DM(EN)	Spread spectrum modulation enable threshold			700		mV
V_DM(CLAMP)	Internal clamp voltage	V_PWM = 0 V, R_RAMP = 200 kΩ		1.25		V
GATE DRIVER (GATE)
R_GH	Gate driver high side resistance	I_GATE = –10 mA		5.4	11.2	Ω
R_GL	Gate driver low side resistance	I_GATE = 10 mA		4.3	10.5	Ω
CURRENT SENSE (IS)
V_IS(LIMIT)	Current limit threshold	V_DIM/PWM = 5 V, R_RAMP = 249 kΩ	230.6	250	270	mV
V_IS(LIMIT)	Current limit threshold	V_DIM/PWM = 0 V, R_RAMP = 249 kΩ	665	700	735	mV
t_IS(BLANK)	Leading edge blanking time		88	118	158	ns
t_IS(FAULT)	Current limit fault time			35		µs
t_ILMT(DLY)	IS to GATE propagation delay	V_IS pulsed from 0 V to 1 V		78		ns
PWM COMPARATOR AND SLOPE COMPENSATION (SLOPE)
D_MAX	Maximum duty cycle			90		%
V_SLOPE	Adaptive slope compensation	V_CSP = 24 V		410		mV
V_SLOPE(MIN)	Minimum slope compensation output voltage	V_CSP = 0 V		72		mV
V_LV	IS to COMP level shift voltage	No slope compensation added	1.42	1.60	1.82	V
I_LV	IS level shift bias current	No slope compensation added		17		µA
CURRENT SENSE AMPLIFIER (CSP, CSN)
V_(CSP-CSN)	Current sense thresholds	V_CSP = 14 V, V_IADJ = 3 V	163.4	170.7	177.6	mV
V_(CSP-CSN)	Current sense thresholds	V_CSP = 14 V, V_IADJ = 1.4 V	95.83	100.5	103.85	mV
CS_(BW)	Current sense unity gain bandwidth			500		kHz
G_CS	Current sense amplifier gain	G = V_IADJ/V_(CSP-CSN)		14
K_(OCP)	Ratio of over-current detection threshold to analog adjust voltage	K _(OCP) = V_(OCP-THR)/V_IADJ	1.46	1.5	1.61
I_CSP(BIAS)	CSP bias current	V_CSN = 14.1 V, V_CSP = 14 V		107		µA
I_CSN(BIAS)	CSN bias current	V_CS_N = 14.1 V, V_CSP = 14 V		110		µA
FAULT INDICATOR (FLT)
R_(FLT)	Open-drain pull down resistance			241		Ω
t_{(FAULT_TMR)}	Fault timer		24	36	48	ms
CURRENT MONITOR (IMON)
I_IMON(SRC)	IMON source current	V_(CSP-CSN) = 150 mV, V_IMON = 0 V			144	µA
V_IMON(CLP)	IMON output voltage clamp		3.2	3.7	4.2	V
V_IMON(OS)	IMON buffer offset voltage		–7.2	0	8.5	mV
ANALOG ADJUST (IADJ)
V_IADJ(CLP)	IADJ internal clamp voltage	I_IADJ = 1 µA	2.29	2.40	2.55	V
I_IADJ(BIAS)	IADJ input bias current	V_IADJ < 2.2 V		10.5		nA
R_IADJ(LMT)	IADJ current limiting series resistor	V_IADJ > 2.6 V		12		kΩ
ERROR AMPLIFIER (COMP)
g_M	Transconductance			121		µA/V
I_COMP(SRC)	COMP current source capacity	V_IADJ = 1.4 V, V_(CSP-CSN) = 0 V		130		µA
I_COMP(SINK)	COMP current sink capacity	V_IADJ = 0 V, V_(CSP-CSN) = 0.1 V		130		µA
EA_(BW)	Error amplifier bandwidth	Gain = –3 dB		5		MHz
V_COMP(RST)	COMP pin reset voltage			100		mV
R_COMP(DCH)	COMP discharge FET resistance			246		Ω
SOFT-START (SS)
I_SS	Soft-start source current		7	10	12.8	µA
V_{SS(UVP_EN)}	Soft-start voltage threshold to enable output under-voltage protection			2.4		V
V_SS(RST)	Soft-start pin reset voltage			50		mV
R_SS(DCH)	SS discharge FET resistance			240		Ω
OUTPUT VOLTAGE INPUT (OV)
V_OVP(THR)	Overvoltage protection threshold		1.195	1.228	1.262	V
V_UVP(THR)	Undervoltage protection threshold		81.7	100	115.1	mV
t_(UVP-BLANK)	Undervoltage protection blanking period			4		µs
I_OVP(HYS)	OVP hysteresis current		12	20	27.5	µA
INTERNAL PWM RAMP GENERATOR (RAMP)
I_RAMP	Ramp generator source current		7.75	10	12.73	µA
I_RAMP	Ramp generator sink current		8.24	10	12.41	µA
V_RAMP	Ramp signal peak (high)			3		V
V_RAMP	Ramp signal valley (low)			1		V
PWM INPUT (DIM/PWM)
V_PWM(HIGH)	Schmitt trigger logic level (high threshold)	V_RAMP = 2.0 V		2.0	2.2	V
V_PWM(LOW)	Schmitt trigger logic level (low threshold)	V_RAMP = 2.0 V	1.8	2.0		V
R_PWM(PD)	PWM pull-down resistance			10		MΩ
t_DLY(RISE)	PWM rising to PDRV delay	C_PDRV = 1 nF		294		ns
t_DLY(FALL)	PWM falling to PDRV delay	C_PDRV = 1 nF		326		ns
SERIES P-CHANNEL PWM FET GATE DRIVE OUTPUT (PDRV)
V_PDRV(OFF)	P-channel gate driver off-state voltage	V_CSP = 14 V		14		V
V_PDRV(ON)	P-channel gate driver on-state voltage	V_CSP = 14 V		7.4		V
I_PDRV(SRC)	PDRV sink current	Pulsed		50		mA
R_PDRV(L)	PDRV driver pull up resistance			82		Ω
THERMAL SHUTDOWN
T_SD	Thermal shutdown temperature			175		°C
T_SD(HYS)	Thermal shutdown hysteresis			25		°C

(1) All voltages are with respect to GND unless otherwise noted

6.6 Typical Characteristics

T_A = 25°C, V_IN = 14 V, V_IADJ = 2.2 V, C_VCC = 1 µF, C_COMP = 2.2 nF, R_CS = 100 mΩ, R_T = 20 kΩ, V_PWM = 5 V, no load on GATE and PDRV (unless otherwise noted)