The DMD mirror voltage regulator generates three high-voltage supply rails: DMD_VRESET, DMD_VBIAS, and DMD_VOFFSET. The DMD regulator uses a switching regulator where the inductor is time-shared between all three supplies. The inductor is charged up to a certain current level and then discharged into one of the three supplies. In cases where a supply does not need additional charge, the time slot normally allocated to that supply is skipped and the supplies requiring more charge receive all of the charging time.

For proper operation, specific bulk capacitance values are required for each supply rail. Refer to Electrical Characteristics—Temperature and Voltage Monitors for recommended values for the capacitors. The regulator contains active power down/discharge circuits. To meet timing requirements, total capacitance (actual capacitance, not the nominal) must not exceed these levels by substantial amounts, as defined in Electrical Characteristics—Temperature and Voltage Monitors. Power-down timing should be verified in each specific system design. Too low of a total capacitance will result in excessive ripple on the supply rails which may impact DMD mirror dynamic behavior. Care should be taken to use capacitors that maintain the recommended minimum capacitance over the expected operating device temperature range. Large-size packages are required here that do not lose so much capacitance at high voltages.

Although the average current drawn by the DMD on these supplies is small (10s of mA worst case), the peak currents can be several amps over 10s of nano-seconds. To supply this peak current, the use of small-value, high-frequency decoupling capacitors should be included as close as practical to the DMD power input pins.

Figure 6-31 DMD Voltage Regulator Circuit