JAJSL21 june   2023 TPSI2072-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Example

Varying PCB implementations are possible depending on both the system EMI requirements and the system dielectric withstand testing (HiPot) parameters. The following sections detail the TPSI2072-Q1 EVM with Thermal Optimization with secondary side metallization for optimized thermal performance and the Interlayer Stitch Capacitance Option for EMI and Thermal Optimization.

TPSI2072-Q1 EVM with Thermal Optimization

The TPSI2072-Q1 EVM images below demonstrate a secondary side thermal metallization pattern and internal floating metal that provides thermal relief to the TPSI2072-Q1 during system dielectric withstand testing (HiPot). The TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top Layer 1 shows the top side creepage and clearance considerations.

GUID-20230530-SS0I-HRMR-TJMV-NK4LFG9CHPP5-low.svg Figure 9-12 TPSI2072-Q1 EVM - Component View
GUID-20230530-SS0I-XZDH-MLRV-JQ2FDNQ88L2N-low.svg Figure 9-13 TPSI2072-Q1 EVM - Layer 1
GUID-20230530-SS0I-6TWM-GVCF-4M0GPGFBRZHM-low.svg Figure 9-14 TPSI2072-Q1 EVM - Layer 2
GUID-20230530-SS0I-67B1-T59R-PMKLWZKZBMVC-low.svg Figure 9-15 TPSI2072-Q1 EVM - Layer 3
GUID-20230530-SS0I-LSKR-DV1W-RH2F34HGQQXF-low.svg Figure 9-16 TPSI2072-Q1 EVM - Layer 4
GUID-20230622-SS0I-BD1N-VWX8-XRSJDZFG7RT3-low.svg Figure 9-17 TPSI2072-Q1 EVM - Layer 5
GUID-20230622-SS0I-TNNR-28QX-CWSJ0BLGX8MC-low.svg Figure 9-18 TPSI2072-Q1 EVM - Layer 6
GUID-20221116-SS0I-P5DP-SSFM-FPZNL7VS1KMM-low.svg Figure 9-19 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top Layer 1
GUID-20221116-SS0I-ZS71-WV9H-42THTFGVCWCP-low.svg Figure 9-20 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Inner Layer 2
GUID-20221116-SS0I-3M3P-NCG6-PTG6RGQXXQCP-low.svg Figure 9-21 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Inner Layer 3
GUID-20221116-SS0I-SVFT-GFF7-JRPNGDXKQBSB-low.svg Figure 9-22 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Bottom Layer 4

Interlayer Stitch Capacitance Option for EMI and Thermal Optimization

The layout example below demonstrates an EMI optimized and thermally optimized PCB Design for high voltage switching applications. The overlapping metal layers beneath the TPSI2072-Q1 form an interlayer stitching capacitance between the primary side ground and the SM pin and increase the board copper content, improving the thermal performance for dielectric withstand testing (HiPot). Metal islands on the S1, SM, and S2 pins on the top side and inner layers further improve the thermal performance. Care should be taken to maintain both the vertical and horizontal interlayer dielectric (ILD) spacings between high voltage terminals required by the system.

GUID-20230530-SS0I-ND3T-KHTG-K7N60MBPS5TM-low.svg Figure 9-23 TPSI2072-Q1 Layout with Interlayer Stitch Capacitance: Top Layer (1)
GUID-20230530-SS0I-N4PJ-K62W-JB6P2CQJJLZK-low.svg Figure 9-24 TPSI2072-Q1 Layout with Interlayer Stitch Capacitance: Inner Layer (2,4)
GUID-20230530-SS0I-T28Q-X0RJ-90CJVS3FGV1T-low.svg Figure 9-25 TPSI2072-Q1 Layout with Interlayer Stitch Capacitance: Inner Layer (3)