JAJSL21 june 2023 TPSI2072-Q1
PRODUCTION DATA
9.4.2 Layout Example
Varying PCB implementations are possible depending on both the system EMI requirements and the system dielectric withstand testing (HiPot) parameters. The following sections detail the TPSI2072-Q1 EVM with Thermal Optimization with secondary side metallization for optimized thermal performance and the Interlayer Stitch Capacitance Option for EMI and Thermal Optimization.
TPSI2072-Q1 EVM with Thermal Optimization
The TPSI2072-Q1 EVM images below demonstrate a secondary side thermal metallization pattern and internal floating metal that provides thermal relief to the TPSI2072-Q1 during system dielectric withstand testing (HiPot). The TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top Layer 1 shows the top side creepage and clearance considerations.
Figure 9-12 TPSI2072-Q1 EVM - Component View
Figure 9-13 TPSI2072-Q1 EVM - Layer 1
Figure 9-14 TPSI2072-Q1 EVM - Layer 2
Figure 9-15 TPSI2072-Q1 EVM - Layer 3
Figure 9-16 TPSI2072-Q1 EVM - Layer 4
Figure 9-17 TPSI2072-Q1 EVM - Layer 5
Figure 9-18 TPSI2072-Q1 EVM - Layer 6
Figure 9-19 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:
Top Layer 1
Figure 9-20 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:
Inner Layer 2
Figure 9-21 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:
Inner Layer 3
Figure 9-22 TPSI2072-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:
Bottom Layer 4Interlayer Stitch Capacitance Option for EMI and Thermal Optimization
The layout example below demonstrates an EMI optimized and thermally optimized PCB Design for high voltage switching applications. The overlapping metal layers beneath the TPSI2072-Q1 form an interlayer stitching capacitance between the primary side ground and the SM pin and increase the board copper content, improving the thermal performance for dielectric withstand testing (HiPot). Metal islands on the S1, SM, and S2 pins on the top side and inner layers further improve the thermal performance. Care should be taken to maintain both the vertical and horizontal interlayer dielectric (ILD) spacings between high voltage terminals required by the system.
Figure 9-23 TPSI2072-Q1 Layout with Interlayer Stitch Capacitance:
Top Layer (1)
Figure 9-24 TPSI2072-Q1 Layout with Interlayer Stitch Capacitance:
Inner Layer (2,4)
Figure 9-25 TPSI2072-Q1 Layout with Interlayer Stitch Capacitance:
Inner Layer (3)