JAJSL21 データシート

Insulation Resistance Monitoring

In high voltage applications such as electric vehicle systems, the high voltage battery pack is intentionally isolated from the chassis domain of the car to protect the driver and prevent damage to electrical components. These systems actively monitor the integrity of this insulation to ensure the safety of the system throughout its lifetime. This active monitoring is referred to as insulation resistance monitoring (also known as isolation check, insulation check, isolation monitoring, insulation monitoring, and residual current monitoring (RCM)) and is performed by measuring the resistances from each of the battery terminals to the chassis ground, illustrated below as R_ISOP and R_ISON.

Figure 9-1 Insulation Resistance Model

There are multiple design architectures using the TPSI2072-Q1 to measure these insulation resistances, R_ISOP and R_ISON. Some architectures employ a microcontroller that performs measurements from the high voltage domain, which will be referred to in this document as the Battery V- Reference architecture. Others use a microcontroller in the low voltage domain, which will be referred to in this document as the Chassis Ground Reference architecture. The primary difference between the two architectures is the node that the MCU uses as its GND reference. An example of a Battery V- MCU is the BQ79631-Q1 UIR sensor.

Figure 9-2 Different MCU ADC Reference Examples

The two following sections demonstrate the measurement algorithms and the systems of equations used to calculate the isolation resistances using each architecture.

Battery V- Reference Example

A Battery V- Reference architecture is shown below with the TPSI2072-Q1 illustrated as a switch (SW1 and SW2). SW2 initiates a connection between the chassis and PACK- and enables the measurement path to the ADC. SW1 initiates a connection between the chassis and the PACK+. RDIV1 and RDIV2 form a divider which scales the measured voltages down to the appropriate ADC range.

Figure 9-3 Battery V- Reference Architecture

Two ADC measurements must be taken in order to obtain enough information to calculate the two unknown isolation resistances. The first measurement is taken with SW1 open and SW2 closed. The second measurement is taken with SW1 closed and SW2 closed. With these two measurements it is possible to solve the system of equations and calculate R_ISOP and R_ISON.

In the following example the voltage on the chassis ground is arbitrarily referred to as V_RISONx.

For the first ADC measurement SW2 is closed as shown below and the following equations relate the ADC voltage to the other parameters in the system in this condition:

V_ADC1 measurement 1: SW1 open, SW2 closed

Equation 1.

V_{R I S O N 1} = V_{P A C K} \times \frac{R_{I S O N} | | (R_{D I V 1} + R_{D I V 2})}{R_{I S O P} + (R_{I S O N} | | R_{D I V 1} + R_{D I V 2})}

Equation 2.

V_{A D C 1} = V_{R I S O N 1} \times \frac{R_{D I V 2}}{R_{D I V 1} + R_{D I V 2}}

Figure 9-4 Battery V- Reference Switch Positions for ADC1 Measurement

For the second ADC measurement SW1 and SW2 are closed as shown below and the following equations relate the ADC voltage to the other parameters in the system in this condition:

V_ADC2 measurement 2: SW1 closed, SW2 closed

Equation 3.

V_{R I S O N 2} = V_{P A C K} \times \frac{R_{I S O N} | | (R_{D I V 1} + R_{D I V 2})}{(R_{I S O P} | | R_{3}) + (R_{I S O N} | | (R_{D I V 1} + R_{D I V 2})}

Equation 4.

V_{A D C 2} = V_{R I S O N 2} \times \frac{R_{D I V 2}}{R_{D I V 1} + R_{D I V 2}}

Figure 9-5 Battery V- Reference Switch Positions for ADC2 Measurement

Chassis Ground Reference Example

A Chassis Ground Reference architecture is shown below. SW1 and SW2 initiate connections to the PACK+ and PACK- and enable the measurement paths to the ADC. RDIV1, RDIV3, and RDIV4 scale the measured voltages down to the appropriate ADC ranges.

This first measurement is taken with SW1 closed and SW2 open and the second measurement is taken with SW1 open and SW2 closed.

VADC1: SW1 closed, SW2 open

Equation 5.

V_{A D C 1} = V_{R D I V 3} = V_{P A C K} \frac{(R_{I S O P} | | (R_{D I V 1} + R_{D I V 3}))}{(R_{I S O P} | | (R_{D I V 1} + R_{D I V 3}) + R_{I S O N})} \times \frac{R_{D I V 3}}{R_{D I V 1} + R_{D I V 3}}

VADC2: SW1 open, SW2 closed

Equation 6.

V_{A D C 2} = V_{R D I V 3} = - V_{P A C K} \frac{(R_{I S O N} | | (R_{D I V 3} + R_{D I V 4}))}{(R_{I S O N} | | (R_{D I V 3} + R_{D I V 4})) + R_{I S O P})} \times \frac{R_{D I V 3}}{R_{D I V 3} + R_{D I V 4}}

Figure 9-6 Chassis Ground Reference Switch Positions for ADC1 Measurement

Figure 9-7 Chassis Ground Reference Switch Positions for ADC2 Measurement

Battery V- Reference and Chassis Ground Reference Architectures with the TPSI2072-Q1

The circuits in Figure 9-8 and Figure 9-9 demonstrate how to connect the TPSI2072-Q1 as a switch in each of the architectures above.

Figure 9-8 TPSI2072-Q1 Insulation Resistance Monitoring – Battery V- Reference

Figure 9-9 TPSI2072-Q1 Insulation Resistance Monitoring – Chassis Ground Reference

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

サーマルパッド・メカニカル・データ

発注情報

9.2 Typical Application

Insulation Resistance Monitoring

Battery V- Reference Example

Chassis Ground Reference Example

Battery V- Reference and Chassis Ground Reference Architectures with the TPSI2072-Q1