JAJSL21 june   2023 TPSI2072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values are measured at TJ = 25°C, VVDD = 5 V, VEN1,EN2 = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PRIMARY SIDE SUPPLY (VDD)
VUVLO_R VDD undervoltage threshold rising VDD rising

 4 4.2 4.4 V
VUVLO_F VDD undervoltage threshold falling VDD falling 3.9 4.1 4.3 V
VUVLO_HYS VDD undervoltage threshold hysteresis 40 100 150 mV
IVDD_ON_S VDD current, single channel powered on VEN1 = 5 V, VEN2 = 0 V OR VEN1 = 0 V, VEN2 = 5 V, TJ = 25°C 5 6 mA
VEN1 = 5 V, VEN2 = 0 V OR VEN1 = 0 V, VEN2 = 5 V, –40°C ≤ TJ ≤ 150°C 5 6.5 mA
IVDD_ON VDD current, both channels powered on VEN1,EN2 = 5 V, TJ = 25°C 9 11 mA
VEN1,EN2 = 5 V, –40°C ≤ TJ ≤ 150°C 9 12 mA
IVDD_OFF VDD current, 5 V, device powered off VVDD = 5 V, VEN1,EN2 = 0 V, TJ = 25°C 3.5 8 µA
VVDD = 5 V, VEN1,EN2 = 0 V, TJ = 105°C 4.5 11 µA
VVDD = 5 V, VEN1,EN2 = 0 V, TJ = 125°C 5.2 16 µA
VVDD = 5 V, VEN1,EN2 = 0 V, –40°C ≤ TJ ≤ 150°C 30 µA
VDD current, 20 V, device powered off VVDD = 20 V, VEN1,EN2 = 0 V, TJ = 25°C 8 10.5 µA
VVDD = 20 V, VEN1,EN2 = 0 V, TJ = 105°C 10 17
VVDD = 20 V, VEN1,EN2 = 0 V, TJ = 125°C 11 25
VVDD = 20 V, VEN1,EN2 = 0 V, –40°C ≤ TJ ≤ 150°C 40
FET CHARACTERISTICS (S1, S2, SM)
RDSON On resistance, S1-SM or SM-S2 IS1,S2 = 2 mA, TJ = 25°C 65 90 Ω
IS1,S2 = 2 mA, TJ = 85°C 88 120
IS1,S2 = 2 mA, TJ = 105°C 96 125
IS1,S2 = 2 mA, TJ = 125°C 105 140
IS1,S2 = 2 mA, –40°C ≤ TJ ≤ 150°C 150
IOFF Off leakage, S1-SM or SM-S2, 500 V V = +/–500 V, TJ = 25°C .02 0.1 µA
V = +/–500 V, TJ = 85°C 0.3
V = +/–500 V, TJ = 105°C 1
V = +/–500 V, TJ = 125°C 4
V = +/–500 V, –40°C ≤ TJ ≤ 150°C 20
Off leakage, S1-SM or SM-S2, 600 V V = +/–600 V, TJ = 25°C .02 0.1 µA
V = +/–600 V, TJ = 85°C 0.5
V = +/–600 V, TJ = 105°C 1.5
V = +/–600 V, TJ = 125°C 6
V = +/–600 V, –40°C ≤ TJ ≤ 150°C 50
VAVA Avalanche voltage  IO = 10 µA, TJ = 25°C 650 770 V
IO = 100 µA, TJ = 150°C 650 770
COSS S1, S2 capacitance VS1,S2,SM = 0 V, F = 1 MHz 150 pF
COSS_SM SM capacitance VSM,S1,S2 = 0 V, F = 1 MHz 300 pF
LOGIC-LEVEL INPUT (EN1, EN2)
VIL Input logic low voltage 0.0 0.8 V
VIH Input logic high voltage 2.1 20.0 V
VHYS Input logic hysteresis 100 250 300 mV
IIL Input logic low current VEN1,EN2 = 0 V –1 1 µA
VEN1,EN2 = 0.8 V 2 4 6.5 µA
IIH Input logic high current VEN1,EN2 = 5 V 10 25 50 µA
VEN1,EN2 = 20 V 100 175 350 µA
IVDD_FS VDD fail-safe current VEN1,EN2 = 20 V, VVDD = 0 V –0.1 0 0.1 µA
RPD Pulldown resistance Two point measurement, VEN1,EN2 = 0.5 V and VEN1,EN2 = 0.8 V 100 200 350 kΩ
NOISE IMMUNITY
CMTI Common-mode transient immunity |VCM| = 1000 V 100.0 V/ns